演講公告
主題 演講者 日期 時間 地點
Phyiscal Unclonable Function - A Burgeoning Technology in Hardware Security Prof. Chip-Hong Chang 2017-10-03 10:00 電機二館144室
Phyiscal Unclonable Function - A Burgeoning Technology in Hardware Security 演講者:Prof. Chip-Hong Chang|School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
時間:Date:2017-10-03|TIme:10:00
地點:電機二館144室
主辦單位:台大電子所
協辦單位:台大系統晶片中心
聯絡人:邱玉霜
聯絡電話:33663718
演講內容:

Summary:

 

Severe security threats and alerts associated with the use of smart devices have drawn increasing public attentions since the inception of Internet of Things (IoT) in late 1990s. The industry projection of 30 billion connected devices by 2020 with the booming of IoT implies a 300 million strong army waiting to launch a massive destruction if only one percent of them are malicious or fake hardware. Because IoT is a network of heterogeneous “things” that are not customarily associated with the internet, the existing forms of supply-chain tagging or unique identity used for authentication of devices connected to the internet can be easily compromised to create attacks that could introduce catastrophic economic and safety treats. As most IoT devices rely on sensor data to acquire information about users and their environment, the leakage of device identities may also leak physical locations and movements, which can be utilized for grievous intelligent and criminal attacks.

 

In this light, silicon Physical Unclonable Function (PUF), a burgeoning technology rooted in 2002, emerges as an inexpensive security primitive to overcome the device tagging problem by its radically different way of generating and processing secret keys in security hardware. The security of PUF rests in the intrinsic complexity and irreproducibility of a random physical disorder system instead of a hard-to-solve mathematical problem. Device signature generated by PUF cannot be physically replicated even by the original manufacturer with the same photolithography masks due to the uncontrollable nature of manufacturing process variations. As the secret information can only be generated by querying the PUF device when it is powered on, active manipulation of circuit structure will cause dysfunction of challenge-response mechanism and destroy the secret.

 

As unique and unclonable chip identifiers, PUFs find its niche in active hardware metering, which enables chip designers to lock and unlock the circuit functionality to gain post-fabrication control of their intellectual property and clone detection. Besides, as chip makers are blazing new path for semiconductors to replace the plain CMOS process technology in the next decade. The rich variety of post-CMOS technologies, such as Phase Change Memory and Spin Transfer Torque Magnetic Random Access Memory, offer different challenges and opportunities to derive new PUF systems with atypical security features and performances. Last but not least, sensors are integral parts of an IoT ecosystem for life-changing applications. Direct integration of PUF credentials into sensor circuitry or sensing data without compromising the original sensing operations holds strong promises in influencing the technological development of hardware security in IoT.

 

A rapid development of PUFs was witnessed in the late 2000s with leapfrog advancement towards their quality enhancement. This effort to overcome the mediocre practicality of ordinary PUFs has a positive impact towards their application development and commercialization. Meanwhile, the commercial viability of PUFs as a security token for device identification has incentivized their attacks. With enhanced speed and precision of measurements made more affordable, side channel analysis is becoming more reachable to recover the integrated secret of the “black box” PUF. The blossoming of machine learning has also led to myth-breaking successes over the last few years in accurately predicting the ``unpredictable'' responses and physically cloning the ``unclonable'' PUFs. Identifying the vulnerabilities and new threat landscapes of existing PUF structures has been an active ongoing research effort. Understanding the underpinning of these attacks will impel countermeasures to undermine their chance of success beyond the complexity that makes them possible in the first place.

 

As we usher PUF into its 15th anniversary, it is time to review the advancements of PUF over the past decade. Besides classical PUF structures and their applications, this seminar will address new breed of PUFs derived from emerging non-volatile memories and vision sensors. 

 

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Circuit Design in Nano-Scale CMOS Technologies Dr. Kevin Zhang 張曉強副總經理 2017-09-27 10:00 台大電機二館105室
Circuit Design in Nano-Scale CMOS Technologies 演講者:Dr. Kevin Zhang 張曉強副總經理|台積公司設計暨技術平台組織
時間:Date:2017-09-27|TIme:10:00
地點:台大電機二館105室
主辦單位:台大電子所
協辦單位:台大系統晶片中心
聯絡人:邱玉霜
聯絡電話:33663718
演講內容:

講者簡介

Dr. Kevin Zhang currently serves as Vice President of Design and Technology Platform where he is responsible to advanced memories, analog, mixed-signal, and RF circuits and IP development. Prior to joining TSMC in November 2016, he was Vice President of Technology and manufacturing Group and Director of Circuit Technology at Intel, where he was responsible to the development of process design rules, circuit & device modeling, digital libraries, key analog and mixed-signal circuits. He led the development of embedded memory technologies from 90nm to 10nm at Intel, including SRAM, eDRAM, eFuse and future memories. He was also responsible to the design and validation of lead vehicles for process technology development at Intel. Dr. Zhang was elected as Intel Fellow in 2005 and led his teams to win 5 Intel Achievement Awards, the highest technical accomplishments at the company.

 

Dr. Zhang has published more than 80 papers at international conferences and in technical journals and is the editor of Embedded Memory for Nano-Scale VLSIs, published by Springer in 2009. He holds 55 U.S. patents in the field of integrated circuit technology. Dr. Zhang was the 2016 International Solid-State Circuit Conference (ISSCC) Program chair and serves on IEEE VLSI Executive Committee. He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE). He received his bachelor's degree from Tsinghua University in Beijing and his Ph.D. from Duke University, both in electrical engineering.

演講大綱

The relentless pursuit of Moore's law by semiconductor industry has led the feature size of CMOS transistor well into nano-scale regime. Deeply scaled technologies have created many new challenges for circuit design, e.g., variation, and voltage head-room. In this presentation, an overview of today's technology landscape will be presented first, including major innovations that have kept the Moore's law continue. Then the focus will be on how to address scaling challenges with novel circuit design techniques, ranging from digital to memory, to analog, and to mixed signals. A number of real design examples will be used to illustrated the new design concept.

A central theme throughout the presentation will be a comprehensive view that technology and design will need to be co-optimized in order to meet the complexity of future product requirements.

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[專題演講]科技創新在緊急應變的角色 石富元醫師 2017-09-25 13:30 博理館113
[專題演講]科技創新在緊急應變的角色 演講者:石富元醫師|臺大醫院
時間:Date:2017-09-25|TIme:13:30
地點:博理館113
主辦單位:電子所
協辦單位:
聯絡人:袁佳琪
聯絡電話:33663530
演講內容:

臺大醫院 石富元醫師將與各位分享

『科技創新在緊急應變的角色』

 

大綱

•緊急應變救護醫療的基本原則及模式

•科技在緊急應變管理的應用與困難

•緊急應變管理的基本概念認識

•科技創新在緊急應變中一些可能發展的方向

 

歡迎有興趣的師長同學一同前來參加

謝謝

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[專題演講]106年度第一學期專題演講課表 電子所專題演講 2017-09-18 13:30 博理館113
[專題演講]106年度第一學期專題演講課表 演講者:電子所專題演講|
時間:Date:2017-09-18|TIme:13:30
地點:博理館113
主辦單位:電子所
協辦單位:
聯絡人:袁佳琪
聯絡電話:33663530
演講內容:

電子所106年度第一學期專題演講講者名單

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[專題演講]不甘寂寞-電機人的舞台之路 楊金源教授 2017-09-18 13:30 博理113
[專題演講]不甘寂寞-電機人的舞台之路 演講者:楊金源教授|國立臺北藝術大學
時間:Date:2017-09-18|TIme:13:30
地點:博理113
主辦單位:電子所
協辦單位:
聯絡人:袁佳琪
聯絡電話:33663530
演講內容:

國立臺北藝術大學  楊金源教授將與各位分享

『不甘寂寞-電機人的舞台之路』

歡迎有興趣的師長同學一同前來參加,

謝謝

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[EDA Seminar] 2017/9/18, Dr. Chung-Yu Wu, The Design of CMOS-SOC-Based Closed-Loop Epileptic Seizure Control System and Its Clinical Applications 基於互補式金氧半晶片系統之閉迴路癲癇控制系統設計及其臨床應用 吳重雨教授 2017-09-18 15:30 博理館101演講廳
[EDA Seminar] 2017/9/18, Dr. Chung-Yu Wu, The Design of CMOS-SOC-Based Closed-Loop Epileptic Seizure Control System and Its Clinical Applications 基於互補式金氧半晶片系統之閉迴路癲癇控制系統設計及其臨床應用 演講者:吳重雨教授|國立交通大學
時間:Date:2017-09-18|TIme:15:30
地點:博理館101演講廳
主辦單位:電子所EDA組、生醫電資所
協辦單位:
聯絡人:黃小姐
聯絡電話:
演講內容:

講題:The Design of CMOS-SOC-Based Closed-Loop Epileptic Seizure Control System and Its Clinical Applications

   基於互補式金氧半晶片系統之閉迴路癲癇控制系統設計及其臨床應用

講者:吳重雨教授 | 國立交通大學講座教授、生醫電子轉譯研究中心主持人

時間:2017/9/18(一) 15:30-16:30

地點:博理101演講廳

 

Abstract:

Epilepsy, the common neurological disorder, afflicts about 1% of world’s population. Epileptic seizures are caused by sudden excessive electrical discharges in a group of cortical neurons. Currently, numerous anti-epileptic drugs are available for seizure control. However, there are still nearly one-third of the patients remain either drug-resistant or develop limiting adverse effects. The alternative and effective clinical treatment for drug-resistant epilepsy is the resection surgery of removing the epileptogenic zone or the implantation of neuromodulators.

Recently, implantable devices with closed-loop electrical stimulation for epileptic seizure control have been presented as a potential and effective clinical treatment. As shown in clinical data, up to 3mA electrical stimulation on cortical surface at seizure onset sites is required to control human epileptic seizures. However the electrical stimulations in the reported systems could not satisfy the above requirement.

In this presentation, a closed-loop neuromodulation System-on-Chip (SOC) with adjustable 0.5−3mA biphasic current stimulation is described. The SoC is powered wirelessly and bidirectional telemetry is realized through the same pair of coils in ISM band (13.56MHz). The clinical applications of the implantable closed-loop epileptic seizure control system will be presented.

Before the treatment of resection surgery or neuromodulator implant, the patients must take careful pre-surgical brain mapping process to identify the seizure onset zone or determine the most suitable neuro-stimulation parameters. All commercial brain mapping equipment systems are lack of real-time closed-loop electrical stimulation. The proposed brain mapping system for pre-surgical evaluation is the integration of brain wave acquisition, seizure onset detection, closed-loop electrical stimulation, and on-demand electrodes selection for electrical stimulation. The prototype of the proposed equipment will be described.

Finally, future development on closed-loop neuromodulation systems will be discussed.

 

Bio:

Dr. Chung-Yu Wu was born in 1950. He received the M.S. and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1976 and 1980, respectively.

Since 1980, he has served as a consultant to high-tech industry and research organizations and has built up strong research collaborations with high-tech industries. From 1980 to 1983, he was an Associate Professor at National Chiao Tung University. During 1984 to 1986, he was a Visiting Associate Professor in the Department of Electrical Engineering, Portland State University, Portland, OR. Since 1987, he has been a Professor at National Chiao Tung University. From 1991 to 1995, he was rotated to serve as the Director of the Division of Engineering and Applied Science on the National Science Council, Taiwan. From 1996-1998, he was honored as the Centennial Honorary Chair Professor at National Chiao Tung University. He received the National Chair Professorship from Ministry of Education, 2015-2017. Currently, he is a Life Chair Professor at National Chiao Tung University. He has published more than 300 technical papers in international transactions/journals and conferences. He also has 47 patents including 23 U.S. patents. His research interests are implantable biomedical integrated circuits and systems, intelligent bio-inspired sensor systems, RF/microwave communication integrated circuits, neural network, analog/mixed-signal integrated circuits, and nanoelectronics.

Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic Societies. He was a recipient of IEEE Fellow Award in 1998 and Third Millennium Medal in 2000. In Taiwan, he received numerous research awards from Ministry of Education, National Science Council, and professional foundations.

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A 40-Gb/s 14-mW CMOS Wireline Receiver Prof. Behzad Razavi 2017-09-15 17:00 電機二館 R142
A 40-Gb/s 14-mW CMOS Wireline Receiver 演講者:Prof. Behzad Razavi|University of California, Los Angeles
時間:Date:2017-09-15|TIme:17:00
地點:電機二館 R142
主辦單位:臺大—聯發科技無線研究實驗室/國立台灣大學系統晶片中心(SOC)
協辦單位:國立台灣大學電子工程研究所/台灣大學電機工程系/ IEEE SSCS Taipei Chapter
聯絡人:顏小姐
聯絡電話:
演講內容:

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[專題演講] 吳安宇所長 2017-09-11 13:30 博理館113
[專題演講] 演講者:吳安宇所長|電子所
時間:Date:2017-09-11|TIme:13:30
地點:博理館113
主辦單位:電子所
協辦單位:
聯絡人:袁佳琪
聯絡電話:33663530
演講內容:

所長座談

 

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SAR ADC techniques : calibration, efficiency, and references Dr. Pieter Harpe | Assistant Professor 2017-08-07 10:00 電機二館142會議室
SAR ADC techniques : calibration, efficiency, and references 演講者:Dr. Pieter Harpe | Assistant Professor|Eindhoven University of Technology
時間:Date:2017-08-07|TIme:10:00
地點:電機二館142會議室
主辦單位:電子所
協辦單位:
聯絡人:楊小姐
聯絡電話:
演講內容:

Abstract : 

This talk is a combination of three conference presentations and addresses three important aspects of SAR ADC design, all focused on problems that play a role around the SAR ADC’s switched-capacitor DAC. The first part deals with calibration of DAC non-linearity caused by capacitor mismatch. This mismatch limits the resolution that can be achieved with Nyquist-rate SAR ADCs. A background calibration method is presented that can correct these errors with a limited overhead in power and chip area. In the second part of this talk, the switching energy of the DAC is analyzed. Most prior-art is looking at minimizing conversion energy. In this case, a technique is proposed to minimize the reset energy. As shown, this could be applied to a variety of existing switching schemes. The last part of this talk looks at the on-chip generation of the reference voltage that is required for the DAC. By means of sub-threshold design and duty-cycling, a power-efficient reference can be generated to achieve a power-efficient reference-included SAR ADC.

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IEEE DLP Series: CMOS microelectronics for DNA detection using ion-sensitive field effect transistors Prof. Pantelis Georgiou 2017-08-04 10:00 EEII 103
IEEE DLP Series: CMOS microelectronics for DNA detection using ion-sensitive field effect transistors 演講者:Prof. Pantelis Georgiou|Imperial College London
時間:Date:2017-08-04|TIme:10:00
地點:EEII 103
主辦單位:電子所
協辦單位:
聯絡人:林致廷教授
聯絡電話:
演講內容:

Abstract:

In the last decade, we have seen a convergence of microelectronics into the world of healthcare providing novel solutions for early detection, diagnosis and therapy of disease. This has been made possible due to the emergence of CMOS technology, allowing fabrication of advanced systems with complete integration of sensors, instrumentation and processing, enabling design of miniaturized medical device which operate. This has been specifically beneficial for the application areas of DNA based diagnostics and full genome sequencing, where the implementation of chemical sensors known as Ion-Sensitive Field-Effect Transistors (ISFETs) directly in CMOS has enabled the design of large-scale arrays of millions of sensors that can conduct in-parallel detection of DNA. Furthermore, the scaling of CMOS with Moore’s law and the integration capability with microfluidics has enabled commercial efforts to  make full genome sequencing affordable and therefore deployable in hospitals and research labs.

 

Biography

Prof. Pantelis Georgiou currently holds the position of senior lecturer at Imperial college London within the Department of Electrical and Electronic Engineering. He is the head of the Bio-inspired Metabolic Technology Laboratory in the Centre for Bio-Inspired Technology; a multi-disciplinary group that invents, develops and demonstrates advanced micro-devices to meet global challenges in biomedical science and healthcare.

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Ultra low-power analog front-end design Dr. Pieter Harpe | Assistant Professor 2017-07-31 10:00 電機二館142會議室
Ultra low-power analog front-end design 演講者:Dr. Pieter Harpe | Assistant Professor|Eindhoven University of Technology
時間:Date:2017-07-31|TIme:10:00
地點:電機二館142會議室
主辦單位:電子所
協辦單位:
聯絡人:楊小姐
聯絡電話:
演講內容:

Abstract : 

This talk, based on an ISSCC 2015 publication, discusses the design of a nano-power analog front-end including pre-amplification and analog-to-digital conversion. It starts with fundamentals on power-efficiency in analog and mixed-signal circuits. It also describes considerations in terms of low-voltage operation and PVT reliability. After that, the presentation discusses one complete system implementation in more detail, including the amplifier, ADC, biasing stages and clock generation.

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[ICS Seminar]RF and Serdes developments in TSMC 謝正祥副處長、謝協宏副理 2017-06-12 16:30 BL114
[ICS Seminar]RF and Serdes developments in TSMC 演講者:謝正祥副處長、謝協宏副理|台積電
時間:Date:2017-06-12|TIme:16:30
地點:BL114
主辦單位:電子所
協辦單位:臺大SOC中心
聯絡人:王小姐
聯絡電話:
演講內容:

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[專題演講]學【生】 林明進教師 2017-06-05 13:30 博理113
[專題演講]學【生】 演講者:林明進教師|建國中學
時間:Date:2017-06-05|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

建國中學 林明進教師將與各位分享

『學【生】』

歡迎有興趣的師長同學一同前來參加,

謝謝

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Design Considerations of CT-DSM Dr. Juiyuan Tsai 2017-05-31 09:10 電二104
Design Considerations of CT-DSM 演講者:Dr. Juiyuan Tsai|MediaTek
時間:Date:2017-05-31|TIme:09:10
地點:電二104
主辦單位:電子所
協辦單位:電機系
聯絡人:李泰成教授
聯絡電話:
演講內容:

Subject:Design Considerations of CT-DSM

 

Venue:  國立臺灣大學電機二館104會議廳

 

Time: 2017年5月31日(星期三)9:10~12:00

 

Speaker: Dr. Juiyuan Tsai (MediaTek)

 

Abstract :

 

Continuous time delta sigma modulators (CT-DSM) are very key blocks in digital communication, audio and sensor applications. This talk will  talk about why we choose CT-DSM, then the design considerations of CT-DSM and finally the trends in CT-DSM.

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Introduction of ΔΣ Modulator Dr. Su-Hao Wu 2017-05-24 09:10 電二104
Introduction of ΔΣ Modulator 演講者:Dr. Su-Hao Wu|MediaTek
時間:Date:2017-05-24|TIme:09:10
地點:電二104
主辦單位:電子所
協辦單位:電機系
聯絡人:李泰成教授
聯絡電話:
演講內容:

Subject:Introduction of ΔΣ Modulator

 

Venue:  國立臺灣大學電機二館104會議廳

 

Time: 2017年5月24日(星期三)9:10~12:00

 

Speaker: Dr. Su-Hao Wu (MediaTek)

 

Abstract :

This lecture will give an intuitive understanding of a ΣΔ ADC through a top-down system design. ΣΔ architectures and design considerations will be addressed, such as discrete-time, continuous-time, multi-stages modulators, loop stability and mismatching issues.

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SiGe For The Next Generation Electronic and Photonic Devices Dr. Guangrui (Maggie) Xia 2017-05-24 14:30 電機二館142室
SiGe For The Next Generation Electronic and Photonic Devices 演講者:Dr. Guangrui (Maggie) Xia|University of British Columbia
時間:Date:2017-05-24|TIme:14:30
地點:電機二館142室
主辦單位:電子所
協辦單位:
聯絡人:張立成
聯絡電話:
演講內容:

【演講公告】SiGe For The Next Generation Electronic and Photonic Devices

講者:Dr. Guangrui (Maggie) Xia (University of British Columbia)

時間:2017/5/24(三) 14:30~16:00

地點:電機二館142室

演講摘要:

This talk will review the research efforts in Dr. Xia's group in the following areas.

1. SiGe including SiGe:C alloys and Ge are widely used for mobility, strain and energy bandgap engineering in major semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs), hetero-junction bipolar transistors (HBTs), SiGe quantum wells and dots, modulators, and Ge lasers.

When the base material changes from Si to SiGe/SiGe:C alloys or Ge and often with the introduction of stress and dislocations, many mass transport behaviors change including dopant diffusion, segregation and Si-Ge interdiffusion. The addition of carbon, dislocations, stress and Ge makes the physical picture quite complicated. Understanding these phenomena are crucial in the device design and processing of SiGe based devices.

2. Ge has been widely used in photodetectors and electro-absorption modulators. For Si-compatible lasers, Ge can be used as 1) transition layers between common lasing materials such as InGaAs and AlGaAs and Si due to its small lattice mismatch to them and the ease of integration with Si and 2) a lasing material thanks to doping and bandgap engineering.

 ----------------------------------------------------------------------------------------------

Speaker Biography:

She joined the Department of Materials Engineering at the University of British Columbia, Vancouver, Canada in 2008. Dr. Xia is an expert in SiGe materials and devices. Her group has studied extensively on Si-Ge interdiffusion, dopant diffusion and segregation in SiGe and SiGe:C systems for applications in CMOS and HBTs. In recent years, her research interests have expanded to Ge lasers and monolithic III-V laser integration on Si, through-Si-vias (TSVs) for 3D integration of ICs, GaN HEMTs, Raman spectroscopy and 2D materials. 

Dr. Xia has published more than 30 research papers and 10 conference papers in top research journals and conferences. Her studies on Si-Ge interdiffusion have been widely used and implemented in the state-of-the-art process simulation tools including Intel R&D’s in-house process simulation tool, Crosslight Software’s CSUPREMTM, Synopsys’s Sentaurus ProcessTM (the leading commercial 3D process simulation tool in the semiconductor industry) and Lumerical Solutions’ DEVICETM for structure and process design of next generations of semiconductor devices. Dr. Xia has been invited to give research seminars by major semiconductor manufacturing companies including Intel, IBM, Texas Instruments, Analog Devices, and Semiconductor Manufacturing International Corporation. She has been serving as an editor of Materials Science in Semiconductor Processing since 2013.

 

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[專題演講]別再講「竹科 on Sale」了--在新的科技世界,台灣充滿機會 吳炳昌執行長 2017-05-22 13:30 博理113
[專題演講]別再講「竹科 on Sale」了--在新的科技世界,台灣充滿機會 演講者:吳炳昌執行長|奇美電子
時間:Date:2017-05-22|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

奇景光電吳炳昌執行長將至臺大電子所與各位分享

『別再講「竹科 on Sale」了--在新的科技世界,台灣充滿機會』

歡迎有興趣的師長同學一同前來參加,

謝謝

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[EDA Seminar] Overcoming challenges in CRISPR/Cas9 gene editing Dr. Steven Lin 2017-05-22 15:30 BL112
[EDA Seminar] Overcoming challenges in CRISPR/Cas9 gene editing 演講者:Dr. Steven Lin|Institute of Biological Chemistry, Academia Sinica; Institute of Biochemical Sciences, National Taiwan University
時間:Date:2017-05-22|TIme:15:30
地點:BL112
主辦單位:EDA組
協辦單位:電子所
聯絡人:江介宏教授
聯絡電話:
演講內容:

Title: Overcoming challenges in CRISPR/Cas9 gene editing

Speaker: Dr. Steven Lin

Institute of Biological Chemistry, Academia Sinica; Institute of Biochemical Sciences, National Taiwan University

Time: 15:30-16:20, May 22, 2017

Location: Room 112, Barry Lam Hall 

 

Abstract: The CRISPR/Cas9 system is a robust genome editing technology that works in human cells, animals, plants and microbes based on the RNA-programmed DNA cleaving activity of the Cas9 enzyme. This presentation provides a quick overview of the fascinating journey through which the studies of CRISPR microbial immune system rapidly revolutionizes the research in genome and cell biology. We will go over the current development of the CRISPR/Cas9 technology, and the strength and weakness of this system. Through real case studies, we will understand the unsolved problems in CRISPR/Cas9-mediated genome engineering and discuss the challenges to overcome to realize its therapeutic potential. 

 

CV:

 

Steven Lin, Ph.D.

 

Assistant Research Fellow

Institute of Biological Chemistry, Academia Sinica, Taiwan

Institute of Biochemical Sciences, National Taiwan University, Taiwan

 

Education

2006 - 2012 Ph.D., Microbiology, University of Illinois at Urbana-Champaign, USA

2004 - 2006 M.S., Biochemistry, The Ohio State University, USA

1996 - 2001 B.S., Biology, University of British Columbia, Canada

 

 

Research training

2012 - 2015 Postdoctoral fellow, University of California, Berkeley, USA

2004 - 2004 Research assistant, The Ohio State University, USA

2001 - 2003 Research assistant, Academia Sinica, Taiwan

 

Selected publications

1. Schumann K*, Lin S*, Boyer E, Simeonov DR, Subramaniam M, Gate RE, Haliburton GE, Ye CJ, Bluestone JA, Doudna JA, Marson A. (2015) Generation of knock-in primary human T cells using Cas9 ribonucleoproteins. Proc Natl Acad Sci 112:10437. *Co-first author.

2. Lin S, Staahl B & Doudna JA (2014) Enhanced homology-directed human genome engineering by controlled timing of CRISPR/Cas9 delivery. eLife 10.7554/eLife.04766.

3. Pattanayak V, Lin S, Guilinger JP, Ma E, Doudna JA & Liu DR (2013) High-throughput profiling of off-target DNA cleavage reveals RNA-programmed Cas9 nuclease specificity. Nat Biotechnol, 31:839.

4. Lo TW, Pickle CS, Lin S, Ralston EJ, Gurling M, Schartner CM, Bian Q, Doudna JA & Meyer BJ (2013) Precise and Heritable Genome Editing in Evolutionarily Diverse Nematodes Using TALENs and CRISPR/Cas9 to Engineer Insertions and Deletions. Genetics, 195:331.   

5. Agarwal V*, Lin S*, Nair S & Cronan JE (2012) Structure of the enzyme-ACP substrate gatekeeper complex required for biotin synthesis. Proc Natl Acad Sci, 109:17406. *Co-first author.

6. Lin S & Cronan JE (2012) The BioC O-methyltransferase catalyzes methyl esterification of malonyl-acyl carrier protein, an essential step in biotin synthesis. J Biol Chem, 287:37010.

7. Lin S, Hanson RE & Cronan JE (2010) Biotin synthesis begins by hijacking the fatty acid synthetic pathway. Nat Chem Biol, 6:682.

 

 

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IBM Watson: A look at the growth of Cognitive Technologies in industry Dev Mookerjee, Technology Executive 2017-05-16 15:30 德田103(CSIE –R103)
IBM Watson: A look at the growth of Cognitive Technologies in industry 演講者:Dev Mookerjee, Technology Executive|Asia Pacific, IBM Watson
時間:Date:2017-05-16|TIme:15:30
地點:德田103(CSIE –R103)
主辦單位:聯發科技-臺大創新研究中心
協辦單位:
聯絡人:盧小姐
聯絡電話:
演講內容:

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The Future of Intelligent Connected Electrification Vehicle VP Charles C. Huang, 总成副总裁 2017-05-16 14:30 德田103(CSIE –R103)
The Future of Intelligent Connected Electrification Vehicle 演講者:VP Charles C. Huang, 总成副总裁|蔚来汽车电动力(NIO E-powertrain)
時間:Date:2017-05-16|TIme:14:30
地點:德田103(CSIE –R103)
主辦單位:聯發科技-臺大創新研究中心
協辦單位:
聯絡人:盧小姐
聯絡電話:
演講內容:

附加檔案: 無
[專題演講]DRAM Industry & Technology 紀儒興處長 2017-05-15 13:30 博理113
[專題演講]DRAM Industry & Technology 演講者:紀儒興處長|美光科技
時間:Date:2017-05-15|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

美光科技 紀儒興 處長 將至臺大電子所與大家分享

『DRAM Industry & Technology』,

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
[專題演講]工程師故事集: 我在 Stanford 的所見所聞 梁仁尉副處長 2017-05-08 13:30 博理113
[專題演講]工程師故事集: 我在 Stanford 的所見所聞 演講者:梁仁尉副處長|聯詠科技
時間:Date:2017-05-08|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

聯詠科技 梁仁尉 副處長 將至臺大電子所與大家分享

『工程師故事集: 我在 Stanford 的所見所聞』,

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
[專題演講]心理學的跨界與火花: 人類感知的研究與應用 葉素玲教授 2017-05-01 13:30 博理113
[專題演講]心理學的跨界與火花: 人類感知的研究與應用 演講者:葉素玲教授|台大心理學系
時間:Date:2017-05-01|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

台大心理學系 葉素玲 教授將至臺大電子所與大家分享

『心理學的跨界與火花: 人類感知的研究與應用』,

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
[專題演講]當科技遇到藝術-人文創意空間 許素朱(小牛老師)教授 2017-04-24 13:30 博理113
[專題演講]當科技遇到藝術-人文創意空間 演講者:許素朱(小牛老師)教授|臺北藝術大學
時間:Date:2017-04-24|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

臺北藝術大學 許素朱(小牛老師) 教授將與各位分享

『當科技遇到藝術-人文創意空間』

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
Integrated Photonics for the Optics-of-Everything (O2E) Dr. Patrick Yin Chiang 2017-04-13 10:00 電機二館142會議室
Integrated Photonics for the Optics-of-Everything (O2E) 演講者:Dr. Patrick Yin Chiang|Fudan University
時間:Date:2017-04-13|TIme:10:00
地點:電機二館142會議室
主辦單位:電子所
協辦單位:電資學院/電機系
聯絡人:李小姐
聯絡電話:
演講內容:

演講主題: Integrated Photonics for the Optics-of-Everything (O2E)

講員: Dr. Patrick Yin Chiang, 1000-Talents Young Professor, Fudan University

                               CTO, PhotonIC Technologies (Shanghai)

演講時間:4/13(四) 10:00-12:00

演講地點:電機二館142會議室

演講大綱: Big Data, Internet-of-Things, Internet-2020, Deep Learning, Autonomous Vehicles.  All of these cloud-computing applications require exponentially increasing bandwidth, resulting in the recent explosive growth in optical networking.  For these optical interconnects, the energy-consuming microelectronics and silicon photonics inside are the key, as they directly affect the cost, size, power, bandwidth, scalability, and manufacturability. 

 

In this talk, I will describe the cross-disciplinary IC design in my Integrated Photonics group at Fudan University, exploring the frontiers of Datacenter Interconnect using Optoelectronics and Silicon Photonics.  Recent publications will be presented, including WDM-based photonics, 50G PAM-4 interconnects, and CMOS-based 25G laser drivers and transimpedance amplifiers. (ISSCC13-15, OFC15-16, RFIC17)

 

主辦單位:台灣大學電子所

協辦單位:台灣大學電資學院/電機系

附加檔案: 無
[專題演講]最年輕的正教授到十大傑出青年(暫定) 簡韶逸教授 2017-04-10 13:30 博理113
[專題演講]最年輕的正教授到十大傑出青年(暫定) 演講者:簡韶逸教授|臺大電子所
時間:Date:2017-04-10|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

臺大電子所 簡韶逸 教授將與各位分享

『最年輕的正教授到十大傑出青年(暫定)』

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
[專題演講]Life in a Foreign Culture: Study Abroad Experience Sharing 陳柏宏教授 2017-03-27 13:30 博理113
[專題演講]Life in a Foreign Culture: Study Abroad Experience Sharing 演講者:陳柏宏教授|交大電子工程學系
時間:Date:2017-03-27|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

交大電子工程學系 陳柏宏 助理教授將與各位分享

『Life in a Foreign Culture: Study Abroad Experience Sharing 』

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
[NE Seminar]TSIA 2017 Q1 校園巡迴講座系列~國立臺灣大學『宏觀下的半導體與未來的封裝技術』講座 洪松井資深副總 2017-03-27 15:30 博理館113室
[NE Seminar]TSIA 2017 Q1 校園巡迴講座系列~國立臺灣大學『宏觀下的半導體與未來的封裝技術』講座 演講者:洪松井資深副總|日月光半導體
時間:Date:2017-03-27|TIme:15:30
地點:博理館113室
主辦單位:台灣半導體產業協會(TSIA)
協辦單位:國立臺灣大學 電子工程研究所(GIEE, NTU)、日月光半導體( ASE Group)
聯絡人:台灣半導體產業協會|吳素敏資深經理
聯絡電話:
演講內容:

 

TSIA 2017 Q1 校園巡迴講座系列
國立臺灣大學『宏觀下的半導體與未來的封裝技術』講座

 

時間:2017年3月27日 (星期一)下午3:30-4:20

地點:國立臺灣大學 博理館113

講師:日月光半導體 洪松井資深副總

 

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[專題演講]Neural and Behavioral Research in Business School 陳瑀屏助理教授 2017-03-20 13:30 博理113
[專題演講]Neural and Behavioral Research in Business School 演講者:陳瑀屏助理教授|臺大國企系
時間:Date:2017-03-20|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

臺大國企系 陳瑀屏 助理教授將與各位分享

『Neural and Behavioral Research in Business School』

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
[專題演講]Cognitive IoT: Taking Machine Learning to Edge Devices David Brooks 2017-03-13 13:30 博理113
[專題演講]Cognitive IoT: Taking Machine Learning to Edge Devices 演講者:David Brooks|
時間:Date:2017-03-13|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

Prof. David Brooks將至臺大電子所與各位分享

『Cognitive IoT: Taking Machine Learning to Edge Devices』,

Abstract: 

Deep learning methods have transformed many aspects of computing replacing decades-old canonical approaches in many domains. This revolution has been driven by enormous amounts of data, novel machine learning algorithms, and inexpensive, high-performance computing through the cloud. Cognitive IoT is a natural evolution of this technology due to the enormous amount of sensor data and the demand for automated analysis. However, IoT devices are typically tiny computing devices at the far edge of the network, suffering from low compute power, poor communication bandwidth, and intermittent connectivity. Furthermore, privacy concerns may lead users to resist approaches that require their data to be processed in public or private cloud systems. Future IoT devices will need integrated architectural support for accelerating deep learning. This talk presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize deep neural network (DNN) hardware accelerators. Hardware accelerators designed with Minerva can be 8x lower power than conventional DNN accelerators, making it feasible to deploy DNNs in power-constrained IoT and mobile devices. Results from a 28nm silicon implementation will be discussed, including measurements of low-voltage operation and improvements in energy-efficiency. The talk will conclude with some future directions for research in this area.

歡迎有興趣的師長同學一同前來參加,

謝謝

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[EDA Seminar] I’m Starting to See a Pattern Here… 江蕙如教授 2017-03-13 15:30 博理館112室
[EDA Seminar] I’m Starting to See a Pattern Here… 演講者:江蕙如教授|交通大學電子系
時間:Date:2017-03-13|TIme:15:30
地點:博理館112室
主辦單位:EDA組
協辦單位:
聯絡人:江介宏教授
聯絡電話:
演講內容:

Title: I’m Starting to See a Pattern Here…

 

Abstract:

Lithography layout decomposition and layout pattern classification are critical and indispensable processes for today's high performance chip design and manufacturing. In this talk, we present two fast and general algorithms on these topics. We also demonstrate that in addition to solution quality, nice algorithms rely on good data structures for achieving high efficiency.

As the technology node advances, more complex coloring rules are introduced. In the first part, for capturing the essence of multiple patterning layout decomposition (MPLD) with complex coloring rules, we model this problem as an exact cover problem and propose a fast and exact MPLD framework based on augmented dancing links. We also develop special treatments based on the properties of MPLD to expedite the solving. Our method is flexible (considering basic and complex coloring rules, and density balancing) and general (handling arbitrary k-patterning). Our results show that our approach achieved the least number of conflicts and stitches among state-of-the-art works, attained superior efficiency and scalability, and handled complex coloring rules and density balancing well.

Layout pattern classification underlies a variety of design for manufacturability applications. In the second part, we present a fast and general layout pattern classification algorithm. Our clip representation can handle not only rigid area match or edge displacement constraints but also variant edge tolerances and don’t care regions. For achieving small cluster count, our clip clustering follows the natural grouping structure of layout clips. For further enhancing efficiency, we propose two-stage clustering including identical clip merging and Markov clustering with feasibility recovery. Our results show that our algorithm outperforms the reference solution and all winning teams of 2016 CAD contest at ICCAD, delivering the smallest cluster count, fastest runtime, and 100% validity.

 

Bio: Iris Hui-Ru Jiang received the B.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1995 and 2002, respectively. She is currently a Professor with the Department of Electronics Engineering, NCTU and has been a visiting scholar of IBM Austin Research Laboratory from 2013 to 2014. Her current research interests include interaction between logic design and physical synthesis, timing analysis and optimization, physical design optimization, design for manufacturability, and data analytics based design automation.

Dr. Jiang received Best Paper Award Nomination from DAC 2016 and ISPD 2013 and Best in-track Paper from ICCAD 2014. She and her students was the recipient of the First Place Award at the CAD Contest at ICCAD in 2012. Her group has received Awards at the TAU Timing Analysis Contests (5 years in a row since 2013). She was the recipient of the 2011 Chinese Institute of Electrical Engineering Outstanding Young Electrical Engineer Award. She is currently the chair of IEEE CEDA Design Automation Technical Committee (DATC), and organized CAD contest at ICCAD from 2012 to 2014 and CADathlon@ICCAD since 2016. She is currently an associate editor of IEEE TCAD and has served on technical program committees of major EDA conferences, including DAC, ICCAD, ISPD, ASP-DAC, SLIP, and IWLS.

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The Good, The Bad and The Ugly of Clock Tree Synthesis Dr. Wen-Hao Liu 2017-03-08 14:00 博理館217室
The Good, The Bad and The Ugly of Clock Tree Synthesis 演講者:Dr. Wen-Hao Liu|Cadence
時間:Date:2017-03-08|TIme:14:00
地點:博理館217室
主辦單位:電子所、IEEE CEDA
協辦單位:
聯絡人:張耀文教授
聯絡電話:
演講內容:

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[專題演講]From IC to Pokemon 林宗賢副所長 2017-03-06 13:30 博理113
[專題演講]From IC to Pokemon 演講者:林宗賢副所長|臺大電子所
時間:Date:2017-03-06|TIme:13:30
地點:博理113
主辦單位:臺大電子所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

臺大電子所 林宗賢 副所長將與各位分享

『From IC to Pokemon』

歡迎有興趣的師長同學一同前來參加,

謝謝

附加檔案: 無
1.Accuracy balancing for the finite-difference-based solution of the discrete Wigner transport equation 2.Application of the discrete Wigner transport equation to simulation of junctionless gate-all-around silicon nanowire transistors: Issues and preliminary results Ting-wei Tang (湯廷尉)Professor Emeritus 2017-01-23 10:00 博理館 R201
1.Accuracy balancing for the finite-difference-based solution of the discrete Wigner transport equation 2.Application of the discrete Wigner transport equation to simulation of junctionless gate-all-around silicon nanowire transistors: Issues and preliminary results 演講者:Ting-wei Tang (湯廷尉)Professor Emeritus|University of Massachusetts
時間:Date:2017-01-23|TIme:10:00
地點:博理館 R201
主辦單位:電子所
協辦單位:
聯絡人:劉致為教授
聯絡電話:
演講內容:

附加檔案: 無
Logic Synthesis, Technology Mapping, and Arithmetic Circuit Verification Dr. Alan Mishchenko 2017-01-18 10:00 Room 104, EE2 Building
Logic Synthesis, Technology Mapping, and Arithmetic Circuit Verification 演講者:Dr. Alan Mishchenko|UC Berkeley
時間:Date:2017-01-18|TIme:10:00
地點:Room 104, EE2 Building
主辦單位:臺大電子所
協辦單位:臺大電機系
聯絡人:江介宏
聯絡電話:(02)33663685
演講內容:

Speaker:
Dr. Alan Mishchenko of UC Berkeley

Title:
SAT-based Methods: Logic Synthesis and Technology Mapping
 
Abstract:
This presentation focuses on the use of Boolean satisfiability as a computation engine in solving typical problems arising in logic synthesis and technology mapping. In particular, a new SAT-based algorithm is presented to compute canonical irredundant sums-of-products (ISOPs) similar to Minato’s well-known BDD/ZDD-based ISOP computation. In addition, two SAT-based technology mappers are discussed: a functional mapper, which exploits don't-cares of a node in the network, and a structural mapper, which searches the space of all structural covers.  Both mappers take a mapped network and improve it based on a user-specified cost function. The mappers are applicable to both standard-cells and lookup tables.

Slides:
https://people.eecs.berkeley.edu/~alanmi/presentations/satmap03.ppt
 
Title:
A Practical Approach to Arithmetic Circuit Verification
 
Abstract:
This talk focuses on a practical approach for arithmetic logic verification. Arithmetic verification proves that a gate-level circuit (such as multiplier) is equivalent to the specification, or verifies that two gate-level circuits with arithmetic components, are equivalent. The proposed approach is based on structural analysis and reverse-engineering of adder-trees. The approach is fast and does not require polynomial construction. An important assumption made: the gate-level circuits contain the cut-points representing inputs/outputs of full-adders and half-adders constituting adder-trees.
 
Bio:
Alan Mishchenko graduated from Moscow Institute of Physics and Technology, Moscow, Russia, in 1993, and received his Ph.D. degree from Glushkov Institute of Cybernetics, Kiev, Ukraine, in 1997. In 2002, Alan started at University of California, Berkeley, where he is now a Full Researcher. His research interests are in developing computationally efficient methods for logic synthesis and verification.

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[專題演講] Key Technologies for Future Semiconductor Industry 劉致為教授 2016-12-26 13:30 博理館113室
[專題演講] Key Technologies for Future Semiconductor Industry 演講者:劉致為教授|電子工程學研究所
時間:Date:2016-12-26|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

電子所 劉致為 教授將與各位分享

『Key Technologies for Future Semiconductor Industry』

歡迎有興趣的師長一同前來參加,

謝謝

附加檔案: 無
Recent Developments in Visible Light Communication - Applications and SoC Design Prof. C. Patrick YUE 2016-12-20 16:30 電機二館145教室
Recent Developments in Visible Light Communication - Applications and SoC Design 演講者:Prof. C. Patrick YUE|Department of Electronic and Computer Engineering, HKUST
時間:Date:2016-12-20|TIme:16:30
地點:電機二館145教室
主辦單位:IEEE SSCS Taipei Chapter/科技部智慧電子研發成果橋接計畫
協辦單位:電子所
聯絡人:李致毅教授
聯絡電話:
演講內容:

附加檔案: 無
[專題演講] 我的超展開電機之路 賴以威教授 2016-12-19 13:30 博理館113室
[專題演講] 我的超展開電機之路 演講者:賴以威教授|長庚大學
時間:Date:2016-12-19|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

瑞昱半導體 林盈熙 副總將與各位分享

『我的超展開電機之路』

歡迎有興趣的師長一同前來參加,

謝謝

附加檔案: 無
[專題演講] Don't Limit Your Challenges , Challenge Your Limits. 林盈熙副總 2016-12-12 13:30 博理館113室
[專題演講] Don't Limit Your Challenges , Challenge Your Limits. 演講者:林盈熙副總|瑞昱半導體 
時間:Date:2016-12-12|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

瑞昱半導體 林盈熙 副總將與各位分享『Don't Limit Your Challenges , Challenge Your Limits』,

歡迎有興趣的師長一同前來參加,

謝謝

附加檔案: 無
[專題演講] 人工智慧與自然人智慧如何共存共榮?年輕人的出路在哪裡? 許炳堅教授 2016-12-05 13:30 博理館113室
[專題演講] 人工智慧與自然人智慧如何共存共榮?年輕人的出路在哪裡? 演講者:許炳堅教授|長庚大學/台灣半導體產業協會 
時間:Date:2016-12-05|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

長庚大學/台灣半導體產業協會 許炳堅 教授將與各位分享

『人工智慧與自然人智慧如何共存共榮?年輕人的出路在哪裡?』

歡迎有興趣的師長一同前來參加,

謝謝

附加檔案: 無
[專題演講] Introduction to NAND Flash Controller 鄭國義處長 2016-11-28 13:30 博理館113室
[專題演講] Introduction to NAND Flash Controller 演講者:鄭國義處長|群聯電子-研發一處
時間:Date:2016-11-28|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

群聯電子-研發一處 鄭國義處長 將與大家分享

『Introduction to NAND Flash Controller』

歡迎有興趣的師長一同前來參加

謝謝

附加檔案: 無
Multiband Filtering for Future 5G – Design and Synthesis Techniques Based on Hybrid Polynomials Prof. Wong Peng Wen 2016-11-28 15:30 BL113
Multiband Filtering for Future 5G – Design and Synthesis Techniques Based on Hybrid Polynomials 演講者:Prof. Wong Peng Wen|Universiti Teknologi Petronas
時間:Date:2016-11-28|TIme:15:30
地點:BL113
主辦單位:奈米電子組
協辦單位:電子所
聯絡人:劉致為教授
聯絡電話:
演講內容:

附加檔案: 無
[專題演講] 我們的夢想,你們的未來-無線醫用SoC 呂學士教授 2016-11-21 13:30 博理館113室
[專題演講] 我們的夢想,你們的未來-無線醫用SoC 演講者:呂學士教授|電子工程學研究所
時間:Date:2016-11-21|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

電子所 呂學士教授將與大家進行專題演講,

講題為『我們的夢想,你們的未來-無線醫用SoC』

歡迎有興趣的師長一同前來參加

謝謝

附加檔案: 無
[專題演講] 醫療物聯網的最新發展 郭博昭教授 2016-11-14 13:30 博理館113室
[專題演講] 醫療物聯網的最新發展 演講者:郭博昭教授|陽明大學腦科學所 
時間:Date:2016-11-14|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

陽明大學腦科學所 郭博昭教授將與大家分享

『醫療物聯網的最新發展』

歡迎有興趣的師長一同參加,

謝謝

附加檔案: 無
Microwave Radiometry Roles in Remote Sensing – Principle and Applications Dr. Julius C Shu 2016-11-10 11:00 電機二館 105室
Microwave Radiometry Roles in Remote Sensing – Principle and Applications 演講者:Dr. Julius C Shu|
時間:Date:2016-11-10|TIme:11:00
地點:電機二館 105室
主辦單位:MediaTek-NTU Research Center
協辦單位:電子所
聯絡人:盧若鳳小姐
聯絡電話:
演講內容:

附加檔案: 無
Audiovidual Data Mining – A Machine Learning and Big Data Perspective Prof. Chin-Hui Lee 2016-11-07 10:00 電機二館124室
Audiovidual Data Mining – A Machine Learning and Big Data Perspective 演講者:Prof. Chin-Hui Lee|Georgia Institute of Technology
時間:Date:2016-11-07|TIme:10:00
地點:電機二館124室
主辦單位:臺大系統晶片中心
協辦單位:電子所
聯絡人:簡韶逸教授
聯絡電話:
演講內容:

附加檔案: 無
[專題演講] Silicon Photonics for Optical Interconnects 陳陽闓院士 2016-10-31 13:30 博理館113室
[專題演講] Silicon Photonics for Optical Interconnects 演講者:陳陽闓院士|美國工程學院/中研院
時間:Date:2016-10-31|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

Nokia Bell Lab 陳陽闓博士 (中研院院士/美國國家工程院士) , 將與各位分享

『Silicon Photonics for Optical Interconnects』

歡迎有興趣的師長前來參加,

謝謝

附加檔案: 無
[專題演講] 時脈控制器(Timing Controller)在面板扮演的角色與挑戰 陳本欣資深處長 2016-10-24 13:30 博理館113室
[專題演講] 時脈控制器(Timing Controller)在面板扮演的角色與挑戰 演講者:陳本欣資深處長|奇景光電-產品中心三
時間:Date:2016-10-24|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

奇景光電-產品中心三 陳本欣資深處長 將與大家分享

『時脈控制器(Timing Controller)在面板扮演的角色與挑戰』

歡迎有興趣的師長一同參加,

謝謝

附加檔案: 無
■Finding Pareto-Optimal Hardware Designs: IP Core Generation and Active Learning ■Program Generation for Performance Prof. Markus Püschel 2016-10-18 14:00 BL201
■Finding Pareto-Optimal Hardware Designs: IP Core Generation and Active Learning ■Program Generation for Performance 演講者:Prof. Markus Püschel|Head of Computer Science, ETH Zürich, Switzerland
時間:Date:2016-10-18|TIme:14:00
地點:BL201
主辦單位:教育部AP聯盟中心
協辦單位:教育部智慧電子總聯盟中心、臺大SOC中心、臺大電子所
聯絡人:王小姐
聯絡電話:3366-1801
演講內容:

附加檔案: 無
[專題演講] IC設計產業發展趨勢與經驗分享 郭豐榮副處長 2016-10-17 13:30 博理館113室
[專題演講] IC設計產業發展趨勢與經驗分享 演講者:郭豐榮副處長|聯詠科技-移動式產品事業處
時間:Date:2016-10-17|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

聯詠科技-移動式產品事業處 郭豐榮副處長 將與大家分享

『 IC設計產業發展趨勢與經驗分享』,

歡迎有興趣的師長一同參加,

謝謝。

附加檔案: 無
If Moore's Law Ends, What will we do? Prof. Yale N. Patt 2016-10-17 14:00 EE2-141
If Moore's Law Ends, What will we do? 演講者:Prof. Yale N. Patt|The University of Texas at Austin
時間:Date:2016-10-17|TIme:14:00
地點:EE2-141
主辦單位:電子所
協辦單位:
聯絡人:陳少傑教授
聯絡電話:
演講內容:

Title: If Moore's Law Ends, What will we do?

Speaker: Prof. Yale N. Patt, The University of Texas at Austin

Date/Time: Monday Oct. 17, 2-3pm

Room: EE-II-141

 

Abstract

We have been riding a strong wave of greater and greater performance for decades, to some extent due to the combination of Moore's Law and Dennard scaling. But we are told all this is coming to an end, in part because we cannot continue to double the transistor count on the chip and we cannot run these things at higher and higher frequencies. Much of the silliness promised by multicore is just that, and not the answer. So, what are we to do? The answer is simple but none the less daunting. We need to expand our awareness of all aspects of the transformation hierarchy. We actually have done a little of this already. For example, predication happened because the compiler, the ISA, and the microarchitecture all cooperated so it could happen. But we can do more, if we are willing to break the artificial walls in the transformation hierarchy. In this talk I hope to point out some of what we can do, and then ask the obvious question: What must we do to be able to make this happen?

 

Short Bio

Yale Patt is a teacher at The University of Texas at Austin who enjoys equally teaching the 400 student required freshman course for ECE majors and his advanced graduate course in microarchitecture. He is also the Ernest Cockrell, Jr. Centennial Chair in Engineering. He continues to thrive on regular classroom teaching, supervising the research of six PhD students, and consulting on microarchitecture problems in industry. He earned appropriate degrees from reputable universities and has received more than his share of awards for his research and teaching. Details can be found on his home page: www.ece.utexas.edu/~patt. He is the co-author with his former PhD student Professor Sanjay Jeram Patel of the University of Illinois, Urbana-Champaign of "Introduction to Computing: from bits and gates to C and beyond," which reflects his motivated bottom-up approach to learning, the correct way to introduce students to computing.

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An Inductorless Fractional-N Synthesizer Architecture Professor Zhiru Zhang 2016-10-14 17:00 明達館R205
An Inductorless Fractional-N Synthesizer Architecture 演講者:Professor Zhiru Zhang|Cornell University
時間:Date:2016-10-14|TIme:17:00
地點:明達館R205
主辦單位:科技部智慧電子研發成果橋接計畫、IEEE SSCS Taipei Chapter、台大-聯發無線研究實驗
協辦單位:臺大電子所
聯絡人:楊小姐
聯絡電話:
演講內容:

Subject:An Inductorless Fractional-N Synthesizer Architecture

Venue:  明達館R205

Time: 2016年10月14日(星期五) 17:00~18:00

Speaker:Prof. Behzad Razavi (University of California, Los Angeles)

 

Abstract : 

We have previously demonstrated that a wideband type-I integer-N phase-locked loop architecture can achieve  a  bandwidth  close  to  fREF /2,  thereby Suppressing  the  phase  noise  of  ring oscillators to Levels   commensurate  with  2.4-GHz  wireless standards while drawing moderate power. The useful attributes of ring oscillators, such as a wide tuning range and more compact design, motivate us to extend this concept to fractional-N operation as well. However, we face the basic trade-off between the loop bandwidth and the modulator quantization noise contribution, an issue that has severely limited the former even in the presence of various noise cancellation techniques.

Rather than deal with fractional-N issues such as charge pump nonlinearity, DAC gain error and nonlinearity, etc., one can contemplate inserting a noise filter immediately after the feedback divider. We introduce a cascaded synthesizer architecture that incorporates a digital synchronous delay line and an analog noise trap to suppress the quantization noise of the Sigma-Delta modulator. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of -109 dBc/Hz and an integrated jitter of 1.68 psrms.

 

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Design Automation for Software-Defined Reconfigurable Computing Professor Zhiru Zhang 2016-10-12 10:30 BL103
Design Automation for Software-Defined Reconfigurable Computing 演講者:Professor Zhiru Zhang|Cornell University
時間:Date:2016-10-12|TIme:10:30
地點:BL103
主辦單位:臺大電子所、IEEE CEDA Taipei Chapter
協辦單位:
聯絡人:張耀文教授
聯絡電話:
演講內容:

Title: Design Automation for Software-Defined Reconfigurable Computing

Speaker: Professor Zhiru Zhang, Cornell University

Time: 10:30am-11:30am, October 12, 2016 (Wednesday)

Place: BL 103, Barry Lam Hall (博理館), Dept. of EE, National Taiwan University

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談研究生的學習態度 李嗣涔教授 2016-10-03 13:30 博理館113室
談研究生的學習態度 演講者:李嗣涔教授|電子工程學研究所
時間:Date:2016-10-03|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

李嗣涔教授將與大家分享

『談研究生的學習態度』

歡迎有興趣的師長同學一同來參加

謝謝

附加檔案: 無
How to Measure Your Life? 陳良基教授 2016-09-26 13:30 博理館113室
How to Measure Your Life? 演講者:陳良基教授|
時間:Date:2016-09-26|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

政務次長 陳良基 與各位分享

How to Measure Your Life?

歡迎有興趣的師長及同學一同參與!

附加檔案: 無
IC Technology Research Needs 胡正明院士 2016-09-22 10:00 博理201
IC Technology Research Needs 演講者:胡正明院士|University of California Berkeley
時間:Date:2016-09-22|TIme:10:00
地點:博理201
主辦單位:電子所
協辦單位:
聯絡人:吳依倩
聯絡電話:
演講內容:

胡正明院士簡介:

胡正明院士,目前係美國柏克萊加州大學電機系教授。胡院士於1968年自國立臺灣大學電機工程學系畢業,此後赴美留學,先後於1970年及1973年獲得柏克萊加州大學電機工程與計算機科學系之碩士、博士學位。胡院士曾是Celestry Design Technologies, Inc.(思略微電子有限公司)創辦人兼任董事長,更於2001~2004年期間擔任台積電首任技術長。

胡院士係半導體領域之先驅領導者,他終身潛心於研發體積更小、耗電更少、性能更強、更可靠的電腦晶片。胡院士所研發的電腦模擬微電路模式BSIM系列於1996已成為國際標準,至今仍繼續研究更新,並免費供全球使用,以此系列所設計之半導體晶片產值超過數千億美元。此外,半導體產業長期以來使用二維元件結構晶片,而他最新研發成功的全新三維FinFET半導體晶片技術,乃是近50年來半導體的革命性創新技術;目前FinFET晶片已使用於市面最新的蘋果和三星手機、電腦伺服器及其他高性能數位應用。預計未來將為電子資訊產業帶來更大變革。

此外,胡院士之學術成就亦相當卓著,出版專書5本,發表論文超過900篇,並擁有逾100件美國專利;另,胡院士曾獲得之獎項與殊榮眾多,近期於2015年12月榮獲美國「國家技術與創新獎章」(National Medal of Technology and Innovation),此係美國政府對科技創新領域貢獻卓著專家所頒授之最高榮譽獎章,歐巴馬總統於2016年5月於白宮舉行頒獎典禮中並親自頒授獎項。

附加檔案: 無
How to Innovate 我如何創新 胡正明院士 2016-09-22 15:30 博理201
How to Innovate 我如何創新 演講者:胡正明院士|University of California Berkeley
時間:Date:2016-09-22|TIme:15:30
地點:博理201
主辦單位:電子所
協辦單位:
聯絡人:吳依倩
聯絡電話:
演講內容:

 

胡正明院士簡介:

胡正明院士,目前係美國柏克萊加州大學電機系教授。胡院士於1968年自國立臺灣大學電機工程學系畢業,此後赴美留學,先後於1970年及1973年獲得柏克萊加州大學電機工程與計算機科學系之碩士、博士學位。胡院士曾是Celestry Design Technologies, Inc.(思略微電子有限公司)創辦人兼任董事長,更於2001~2004年期間擔任台積電首任技術長。

胡院士係半導體領域之先驅領導者,他終身潛心於研發體積更小、耗電更少、性能更強、更可靠的電腦晶片。胡院士所研發的電腦模擬微電路模式BSIM系列於1996已成為國際標準,至今仍繼續研究更新,並免費供全球使用,以此系列所設計之半導體晶片產值超過數千億美元。此外,半導體產業長期以來使用二維元件結構晶片,而他最新研發成功的全新三維FinFET半導體晶片技術,乃是近50年來半導體的革命性創新技術;目前FinFET晶片已使用於市面最新的蘋果和三星手機、電腦伺服器及其他高性能數位應用。預計未來將為電子資訊產業帶來更大變革。

此外,胡院士之學術成就亦相當卓著,出版專書5本,發表論文超過900篇,並擁有逾100件美國專利;另,胡院士曾獲得之獎項與殊榮眾多,近期於2015年12月榮獲美國「國家技術與創新獎章」(National Medal of Technology and Innovation),此係美國政府對科技創新領域貢獻卓著專家所頒授之最高榮譽獎章,歐巴馬總統於2016年5月於白宮舉行頒獎典禮中並親自頒授獎項。

附加檔案: 無
快快樂樂做研究 張耀文教授 2016-09-19 13:30 博理館113室
快快樂樂做研究 演講者:張耀文教授|電子工程學研究所
時間:Date:2016-09-19|TIme:13:30
地點:博理館113室
主辦單位:電子工程學研究所
協辦單位:
聯絡人:辜小姐
聯絡電話:33663530
演講內容:

此演講將共同探討成為快樂研究生的要訣與經驗,歡迎有興趣的同學一同參加。

附加檔案: 無
Industry Needs and Commercialization Paths Dr. C.Y. (Chun-Yung) Sung, Technical Director 2016-09-09 14:00 博理103室
Industry Needs and Commercialization Paths 演講者:Dr. C.Y. (Chun-Yung) Sung, Technical Director|Adv. Technol., Rotary, Mission & Systems (RMS) Corporate Engineering and Technology Operations (CETO)
時間:Date:2016-09-09|TIme:14:00
地點:博理103室
主辦單位:臺大產學合作總中心、臺大電信所、臺大電機系、臺灣電磁產學聯盟
協辦單位:
聯絡人:劉深淵教授
聯絡電話:
演講內容:

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CMOS-assisted nano-bio interface array for Neurotechnology Prof. Donhee Ham 2016-08-19 11:00 EE2-105
CMOS-assisted nano-bio interface array for Neurotechnology 演講者:Prof. Donhee Ham|Gordon McKay Professor of Applied Physics and EE School of Engineering and Applied Sciences (SEAS) Harvard University
時間:Date:2016-08-19|TIme:11:00
地點:EE2-105
主辦單位:NTU College of Electrical Engineering and Computer Science, MediaTek-NTU Research Center
協辦單位:
聯絡人:盧小姐
聯絡電話:(02)3366-1836
演講內容:

附加檔案: 無
Rethinking “Things” Design - the Missing (Technology) Link in the Internet of Things Massimo AliotoAssociate Professor 2016-07-28 15:00 台大博理館201室
Rethinking “Things” Design - the Missing (Technology) Link in the Internet of Things 演講者:Massimo AliotoAssociate Professor|the ECE Department of the National University of Singapore
時間:Date:2016-07-28|TIme:15:00
地點:台大博理館201室
主辦單位:台大電子所/科技部
協辦單位:台大系統晶片中心 , IEEE SSC, Taipei Chapter.
聯絡人:邱玉霜
聯絡電話:33663718
演講內容:
ABSTRACT:
    The Internet of Things (IoT) has now become a main driver in research and next-generation technology development, and is expected to foster the growth of the semiconductor industry in the next decade or more, as the wave of mobile platforms is reaching its saturation.
In spite of daily announcements of new industrial projects in the IoT domain, the physical nodes that gather sensed data (the “things”) are still technologically immature, and well behind the rest of the IoT infrastructure. This lag has been determined by several daunting challenges in terms of energy efficiency and security under tight cost constraints, as well as a rigid view on the quality of service provided by IoT nodes. Energy efficiency is indeed synonym for node availability and size, whereas cheap chip-level security is a necessary premise to build adequate trust in the minds of potential adopters.
This talk addresses these fundamental issues and sketches a map to move towards the true realization of the physical layer of IoT, and ultimately enable IoT nodes with extreme energy efficiency and unceasing security, in both space (across nodes) and time (in each node). The scalable quality of service in IoT nodes is shown to be a key ingredient to relax the critical design tradeoffs, and generalize the well-known concept of “QoS” that is ubiquitously applied in the Internet of today. A perspective is finally given on the future role of technology and EDA industry in the IoT arena, based on the natural bottom-up (business) pressure that has made the Internet possible in the past. And will make the Internet of Things real in the future, well beyond the current wave of simple smartwatches.
 
BIO:
    Massimo Alioto is Associate Professor at the ECE Department of the National University of Singapore, where he leads the Integrated Circuits and Embedded Systems area (80+ people) and the Green IC group. Previously, he was Visiting Scientist at Intel Labs – CRL (2013), Visiting Professor at the University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL – Lausanne (2007), and Associate Professor at the University of Siena.
He is (co)author of 220+ publications on journals (80, mostly IEEE Transactions) and conference proceedings, and two books with Springer. His primary research interests include ultra-low power VLSI circuits, self-powered/wireless nodes, near-threshold circuits for green computing, energy-quality scalable VLSI circuits, circuits for HW-level security and on-chip learning.
He is currently Associate Editor in Chief of the IEEE Transactions on VLSI Systems. He also serves or has served as Associate Editor of several IEEE and ACM journals. He served as Guest Editor of various journal special issues (e.g., “Ultra-Low Voltage Circuits and Systems for Green Computing” on IEEE TCAS-II). He is/was Technical Program Chair of several IEEE conferences (ICECS, VARI, NEWCAS, ICM), and Track Chair in several others (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM). In the last five years, he has given 50+ invited talks in top universities and leading semiconductor companies. He is/was Distinguished Lecturer (2009-2010) and member of the Board of Governors of the IEEE Circuits and Systems Society (2015-2016). He is an IEEE Fellow.
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IC Technology Research Needs Prof. Chenming Hu 2016-07-08 10:30 EE2-142
IC Technology Research Needs 演講者:Prof. Chenming Hu|University of California Berkeley
時間:Date:2016-07-08|TIme:10:30
地點:EE2-142
主辦單位:電子所
協辦單位:
聯絡人:吳依倩
聯絡電話:
演講內容:

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Himax 的創新策略與台灣產業轉型之路 吳炳昌執行長 2016-06-13 1330 博理館113室
Himax 的創新策略與台灣產業轉型之路 演講者:吳炳昌執行長|奇景光電
時間:Date:2016-06-13|TIme:1330
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於6月13日(一)邀請奇景光電-吳炳昌執行長
至本所演講,演講資訊如下。
 
講者:奇景光電-吳炳昌執行長
講題:Himax 的創新策略與台灣產業轉型之路
日期:6月13日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
Non-linear programming methods for VLSI placement problem Professor Jianli Chen 2016-06-13 15:30 博理館112室
Non-linear programming methods for VLSI placement problem 演講者:Professor Jianli Chen|Fuzhou University
時間:Date:2016-06-13|TIme:15:30
地點:博理館112室
主辦單位:EDA組
協辦單位:電子所
聯絡人:張耀文教授
聯絡電話:
演講內容:
Title: Non-linear programming methods for VLSI placement problem
Lecture: Professor JianliChen, Fuzhou University
Time: 15:30-16:20, June 13, 2016 (Mon)
Place: Room 112, Barry Lam Hall, GIEE, National Taiwan University
 
 
Abstract: The common objective of very large scale integration (VLSI) placement problem is to minimize the total wirelength, which is calculated by the total half-perimeter wirelength(HPWL). Since the HPWL is not differentiable, various differentiable wirelengthapproximation functions have been proposed in nonlinear programming placement methods. The VLSI placement problem is NP-hard, and many placement constraints on a chip must be considered. It is a great challenge to design efficient and effective algorithms for the VLSI placement problem, especially for handling designs with millions of objects. In this talk, from the view of mathematics methods, I will try to discuss the characteristics of VLSI placement problem, and introduce some of our work on this problem.
 
Bio:Dr. JianliChen is currently an Associate Professor at the Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University. He received the B.Sc. degree in information and computing sciences, the M.Sc. degree in computer application technology, and the Ph.D. degree in applied mathematics, all from Fuzhou University, Fuzhou, China, in 2007, 2009, and 2012, respectively. His research interests include optimization theory and applications, and optimization methods for very large scale integration placement. He received Best Paper Award from the International Doctoral Forum on Operations Research and Control Theory in 2011, the first prize in 13th FuJianBest Paper Award in Natural Sciences (2014), and the Distinguished Young Scholars Foundation of FuJianEducational Committee in 2016.
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口語表達特調 李佩雯教授 2016-06-13 16:30 明達館231室
口語表達特調 演講者:李佩雯教授|世新大學口語傳播學系
時間:Date:2016-06-13|TIme:16:30
地點:明達館231室
主辦單位:ICS組
協辦單位:電子所
聯絡人:林宗賢教授
聯絡電話:
演講內容:
講題:口語表達特調
講者:李佩雯教授/世新大學口語傳播學系
日期:2016年06月13日(一)
時間:16:30-17:20
地點:明達館 231室
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走尋轉型的遠見---人文與工程思維 吳泉源副院長 2016-06-06 13:30 博理館113室
走尋轉型的遠見---人文與工程思維 演講者:吳泉源副院長|清大人文社會學院
時間:Date:2016-06-06|TIme:13:30
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於6/6 (一)請講者吳泉源副院長-清大人文社會學院
至本所演講,演講資訊如下。
 
講者:吳泉源副院長-清大人文社會學院
講題:走尋轉型的遠見---人文與工程思維
日期:6月6日(一)
時間:13:30-15:00
地點:博理館113室
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東亞與東南亞民間故事中的生殖意象 楊雨樵先生 2016-06-06 16:30 明達館231室
東亞與東南亞民間故事中的生殖意象 演講者:楊雨樵先生|
時間:Date:2016-06-06|TIme:16:30
地點:明達館231室
主辦單位:電子所ICS組
協辦單位:
聯絡人:邱助教
聯絡電話:
演講內容:

東亞與東南亞民間故事中的生殖意象

講者:楊雨樵
服務單位:專欄作家
日期:2016年06月06日(一)
時間:16:30-17:20
地點:明達館 231室
附加檔案:
Practical considerations in IC design of mobile baseband transceivers 陳奕甫經理 2016-06-04 13:30 博理館112室
Practical considerations in IC design of mobile baseband transceivers 演講者:陳奕甫經理|聯發科技
時間:Date:2016-06-04|TIme:13:30
地點:博理館112室
主辦單位:臺大-聯發科技無線研究實驗室
協辦單位:臺灣大學電子所、臺大系統晶片中心
聯絡人:劉小姐
聯絡電話:
演講內容:
時間:2016.6.4(六)13:30
 
地點:臺灣大學 博理館112室
 
演講題目:
Practical considerations in IC design of mobile baseband transceivers
 
摘要:
The demand for power-efficient multi-mode mobile phones poses challenges to
designers of baseband modems.  These challenges usually involve trade-off among
cost, power, performance, flexibility, time to market, and other properties of
baseband modems during architecture definition and chip design. In this talk,
some examples of the design trade-offs and practical considerations for evaluating
options will be presented.  In addition, observations about trends of recent mobile
communication technology development are shared. The talk and the following Q&A
session will be given in Mandarin.
 
講者簡歷:
陳奕甫
1997 台大電機系畢業
1999 台大電子所ICS 組碩士班畢業
曾任職於 台灣吉悌電信 及 威盛電子
現任職於 聯發科技
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蟑螂生理學—我的土博學思歷程 黃佳欣博士 2016-05-30 1330 博理館113室
蟑螂生理學—我的土博學思歷程 演講者:黃佳欣博士|中央研究院資訊科學所
時間:Date:2016-05-30|TIme:1330
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於5/30 (一)請講者黃佳欣博士-中央研究院資訊科學所
至本所演講,演講資訊如下。
 
講者:黃佳欣博士-中央研究院資訊科學所
講題:蟑螂生理學—我的土博學思歷程
日期:5月30日(一)
時間:13:30-15:00
地點:博理館113室
 
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生命圖靈機(Turing Machine) 黃佑充董事 2016-05-23 13:30 BL113
生命圖靈機(Turing Machine) 演講者:黃佑充董事|創惟科技
時間:Date:2016-05-23|TIme:13:30
地點:BL113
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於5/23 (一)請講者創惟科技-黃佑充董事
至本所演講,演講資訊如下。
 
講者:創惟科技-黃佑充董事
講題:生命圖靈機(Turing Machine)
日期:5月23日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
Design for Manufacturability and Reliability in Extreme Scaling Professor Bei Yu 2016-05-18 16:00 BL201
Design for Manufacturability and Reliability in Extreme Scaling 演講者:Professor Bei Yu|The Chinese University of Hong Kong
時間:Date:2016-05-18|TIme:16:00
地點:BL201
主辦單位:電子所
協辦單位:SOC中心
聯絡人:張耀文教授
聯絡電話:
演講內容:
Title: Design for Manufacturability and Reliability in Extreme Scaling
Speaker: Professor Bei Yu,
The Chinese University of Hong Kong
Time: 16:00-17:30, May 18th, 2016 (Wed)
Place: Room 201, Barry Lam Hall, Dept. of EE, National Taiwan University
 
Abstract: The continuous shrinking of feature sizes for very large scale integrated (VLSI) circuits with advanced lithography has been a holy grail for the semiconductor industry to achieve ever-higher device density and performance with reduced cost per transistor. However, due to the more and more serious manufacturability and reliability issues, this aggressive scaling has been facing severe challenges. Multiple patterning lithography, along with other advanced lithography techniques, e.g., extreme ultraviolet, electron beam, directed self-assembly, are promising solutions to overcome these challenges. In this talk I will introduce our coherent CAD framework to provide multiple patterning lithography manufacturing friendly design. Besides, I will describe our physical verification tool to detect the hotspots, which are lower fidelity patterns on a layout. Integrated with a set of machine learning techniques, our tool is shown to be effective to detect most of the hotspots, and thus be able to enhance the design reliability.
 
Bio: Professor Bei Yu​ ​is currently an Assistant Professor at the Department of Computer Science and Engineering, The Chinese University of Hong Kong. He received the Ph.D degree from Electrical and Computer Engineering, University of Texas at Austin, USA in 2014. His current research interests include design for manufacturability, cyber physical systems, machine learning and combinatorial algorithms with applications in VLSI CAD. He received William J. McCalla Best Paper Award from International Conference on ICCAD in 2013, Best Paper Award from ASPDAC in 2012, three ICCAD contest awards in 2012, 2013 and 2015, IBM Ph.D. Scholarship in 2012, SPIE Education Scholarship in 2013, and EDAA Outstanding Dissertation Award in 2014.
 
 
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A photoreceptor protein functions as a light-driven proton pump 一個功能為光驅動質子泵的感光蛋白質 楊啓伸教授 2016-05-16 13:30 博理館113室
A photoreceptor protein functions as a light-driven proton pump 一個功能為光驅動質子泵的感光蛋白質 演講者:楊啓伸教授|臺大生科所
時間:Date:2016-05-16|TIme:13:30
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於5/16 ()請講者臺大生科所-楊啓伸教授
至本所演講,演講資訊如下。
 
講者:臺大生科所-楊啓伸教授
講題:A photoreceptor protein functions as a light-driven proton pump
一個功能為光驅動質子泵的感光蛋白質
日期:5月16日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
ISSCC 2016 review workshop 闕志達教授等 2016-05-11 14:00 電機二館142、103會議室
ISSCC 2016 review workshop 演講者:闕志達教授等|
時間:Date:2016-05-11|TIme:14:00
地點:電機二館142、103會議室
主辦單位:IEEE SSCS Taipei Chapter、臺大系統晶片中心
協辦單位:臺灣大學電子所、臺灣大學電機系
聯絡人:吳小姐
聯絡電話:02-33663531
演講內容:
Subject:ISSCC 2016 review workshop
Venue: NTU EE-II 142/103
Time: 5/11 PM 2:00~4:00
講者:
      闕志達副院長(Prof. Chiueh)
      Opening / ISSCC Introduction
 
      林宗賢教授(Prof. T-H Lin)
      Trend of Power Conversion and Power Transfer/Harvesting in ISSCC 2016
 
      汪炳穎委員(Mr. P-Y Wang)
      Trade-offs in PLL design and Digital calibration for performance enhancement
 
      of PLLs
      李泰成教授(Prof. T-C Lee)
      Trend of Data Converter in ISSCC 2016
 
      張孟凡教授(Prof. M-F Chang)
      Trend of Memory in ISSCC 2016
 
      楊家驤教授(Prof. C-H Yang)
      Trend of Next-Generation Processing in ISSCC 2016
 
Abstract:
This ISSCC 2016 Review workshop starts with the introduction of ISSCC itself and the “game rule” of ISSCC paper submission. With the basic understanding of ISSCC, five presentations would cover some interesting ISSCC 2016 technical papers on the popular topics, including power, data converter, clock generator, low-power digital and memory design. All of these circuit techniques could be readily applied in the emerging applications, such as IOE (internet of everything), 5G communication and augmented reality. In addition, the design trend of each topic would be illustrated.    
 
一律採上網報名
請掃瞄海報上的QR Code
或至臺大系統晶片中心網頁http://soc.ee.ntu.edu.tw/近期活動訊息進行報名
 
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A Journey Beyond Electrical Engineering 董倫長董事長 2016-05-09 13:30 博理館113室
A Journey Beyond Electrical Engineering 演講者:董倫長董事長|美思科技
時間:Date:2016-05-09|TIme:13:30
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於5/9 (一)請講者美思科技-董倫長董事長
至本所演講,演講資訊如下。
 
講者:美思科技-董倫長董事長
講題:A Journey Beyond Electrical Engineering
日期:5月9日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
Sharing of The prospection of hardware design in future Semiconductor Industry 吳慶杉總經理 2016-05-02 13:30 博理館113室
Sharing of The prospection of hardware design in future Semiconductor Industry 演講者:吳慶杉總經理|聯發科技
時間:Date:2016-05-02|TIme:13:30
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於5/2 (一)請講者聯發科技-吳慶杉總經理
至本所演講,演講資訊如下:
 
講者:聯發科技-吳慶杉總經理
講題:Sharing of The prospection of hardware design in future Semiconductor Industry
日期:5月2日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
記得你是誰! ──生醫電子的啟示錄 吳重雨教授 2016-04-25 13:30 博理館113室
記得你是誰! ──生醫電子的啟示錄 演講者:吳重雨教授|交大電子系
時間:Date:2016-04-25|TIme:13:30
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於4/25(一)請講者記得你是誰!──生醫電子的啟示錄
至本所演講,演講資訊如下:
 
講者:交大電子系-吳重雨教授
講題:記得你是誰!──生醫電子的啟示錄
日期:4月25日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
藝術與科學的共通 郭廣賢總監 2016-04-11 13:30 博理113室
藝術與科學的共通 演講者:郭廣賢總監|亞全顧問有限公司
時間:Date:2016-04-11|TIme:13:30
地點:博理113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
電子所將於4/11(一)請講者輔仁大學應用美術學系-郭廣賢老師
至本所演講,演講資訊如下:
 
講者:輔仁大學應用美術學系-郭廣賢老師(亞全顧問有限公司總監)
講題:藝術與科學的共通
日期:4月11日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
IC設計產業未來發展趨勢與願景 黃依瑋副總經理 2016-03-28 13:30 BL113
IC設計產業未來發展趨勢與願景 演講者:黃依瑋副總經理|瑞昱半導體
時間:Date:2016-03-28|TIme:13:30
地點:BL113
主辦單位:電子所
協辦單位:TSIA
聯絡人:魏小姐
聯絡電話:
演講內容:
講者:瑞昱半導體-黃依瑋副總經理
講題:IC設計產業未來發展趨勢與願景
日期:3月28日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
Brain-inspired Computing: from Hardwares to Applications Dr. Gi-Joon Nam 2016-03-28 15:30 BL112
Brain-inspired Computing: from Hardwares to Applications 演講者:Dr. Gi-Joon Nam|IBM T. J. Watson Research Center
時間:Date:2016-03-28|TIme:15:30
地點:BL112
主辦單位:EDA組
協辦單位:電子所
聯絡人:張耀文教授
聯絡電話:
演講內容:
Title:Brain-inspired Computing: from Hardwares to Applications
Speaker: Dr. Gi-Joon Nam of the IBM T. J. Watson Research Center
Time: 3:30-4:20pm, March 28th, 2016 (Monday)
Place: BL 112

Abstract:
In recent years, there have been significant amount of interests in a new quest in building a brain-inspired machine. In contrast to the prevailing von Neumann architecture that most traditional computers are based on, a brain-inspired machine mimics the operations of the brain’s neuron and synaptic system to replicate the human brain’s talent for learning new tasks. In this talk, we will provide system perspectives of a brain-inspired computer by presenting circuit implementations, software programming models and promising applications.

Bio:
Gi-Joon Nam is a research staff member and manager at the IBM T. J. Watson Research Center. He currently manages the Physical Design department. His group is conducting research on various design automation techniques for high performance computing IBM products such as IBM’s P/Z microprocessors and server chips. Prior to this, he has managed the Optimized Analytics System department at the IBM Austin Research Lab working on the workload optimized systems for big data applications. Gi-Joon has been involved with leading-edge high performance VLSI designs for 15+ years, starting from 130 nm technology nodes to sub-20 nm technologies.
Email: gnam@us.ibm.com
 
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北大X臺大 EECS Matched Talks (上午場-資訊工程領域) 洪一平教授(本校)、查紅彬副院長(北大) 2016-03-23 10:55 博理館201室
北大X臺大 EECS Matched Talks (上午場-資訊工程領域) 演講者:洪一平教授(本校)、查紅彬副院長(北大)|
時間:Date:2016-03-23|TIme:10:55
地點:博理館201室
主辦單位:電資學院
協辦單位:北京大學信息科學技術學院
聯絡人:顏孝純小姐
聯絡電話:33663697
演講內容:
電資學院很榮幸於本月邀請到北京大學信息科學技術學院的教授至本院交流,並與本院教師舉辦雙邊演講活動。
演講主題分為資訊工程及光電工程兩個領域,題目包含3D Reconstruction for Object Modeling and Scene Analysis、Silicon Photonics、Bio-inspired Microlenses for Compact Imaging Systems、Photonics for Environment and Health等議題。
 
歡迎各位學生踴躍報名!
上午場--資訊工程領域: 由本校洪一平教授及北大查紅彬副院長共同演說。
下午場--光電工程領域:由本校林清富教授蘇國棟教授以及北大周治平教授王興軍教授共同演說。
 
日期: 105年3月23日
地點: 博理館201室
上午場: 10:55 入場
下午場: 13:30 入場
 
 
完成線上報名者,當日中午12點可以於場外領取餐盒。報名人次限60名。
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北大X臺大 EECS Matched Talks(下午場-光電工程領域) 林清富教授(本校)、蘇國棟教授(本校)、周治平教授(北大)、王興軍教授(北大) 2016-03-23 13:30 博理館201室
北大X臺大 EECS Matched Talks(下午場-光電工程領域) 演講者:林清富教授(本校)、蘇國棟教授(本校)、周治平教授(北大)、王興軍教授(北大)|
時間:Date:2016-03-23|TIme:13:30
地點:博理館201室
主辦單位:電資學院
協辦單位:北京大學信息科學技術學院
聯絡人:顏孝純
聯絡電話:33663697
演講內容:
電資學院很榮幸於本月邀請到北京大學信息科學技術學院的教授至本院交流,並與本院教師舉辦雙邊演講活動。
演講主題分為資訊工程及光電工程兩個領域,題目包含3D Reconstruction for Object Modeling and Scene Analysis、Silicon Photonics、Bio-inspired Microlenses for Compact Imaging Systems、Photonics for Environment and Health等議題。
 
歡迎各位學生踴躍報名!
上午場--資訊工程領域: 由本校洪一平教授及北大查紅彬副院長共同演說。
下午場--光電工程領域:由本校林清富教授蘇國棟教授以及北大周治平教授王興軍教授共同演說。
 
日期: 105年3月23日
地點: 博理館201室
上午場: 10:55 入場
下午場: 13:30 入場
 
 
完成線上報名者,當日中午12點可以於場外領取餐盒。報名人次限60名。
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人生,就是一場募集的旅程 何威廷主任 2016-03-21 13:30 博理館113室
人生,就是一場募集的旅程 演講者:何威廷主任|勾勾gogo募集平台
時間:Date:2016-03-21|TIme:13:30
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
講者:勾勾gogo募集平台-何威廷負責人
講題:人生,就是一場募集的旅程
日期:3月21日(一)
時間:13:30-15:00
地點:博理館113室
附加檔案:
SAT-based Methods in Logic Synthesis and Technology Mapping Alan MishchenkoResearch Scientist 2016-03-17 11:00 225 EE2
SAT-based Methods in Logic Synthesis and Technology Mapping 演講者:Alan MishchenkoResearch Scientist|UC Berkeley
時間:Date:2016-03-17|TIme:11:00
地點:225 EE2
主辦單位:臺大電子所
協辦單位:臺大電機系
聯絡人:江介宏
聯絡電話:33663685
演講內容:

Abstract: This presentation focuses on the use of Boolean satisfiability as a computation engine in solving typical problems arising in logic synthesis and technology mapping. In particular, a new SAT-based algorithm is presented to compute canonical irredundant sums-of-products (ISOPs) similar Minato’s well-known BDD/ZDD-based ISOP computation. In addition, two SAT-based technology mappers are discussed: a functional mapper, which exploits don't-cares of a node in the network, and a structural mapper, which searches the space of all structural covers.  Both mappers take a mapped network and improve it based on a user-specified cost function. The mappers are applicable to both standard-cells and lookup tables.

Bio: Alan graduated from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 with MS and received his PhD from the Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. From 1998 to 2002 he was an Intel-sponsored visiting scientist at Portland State University. In 2002, he joined the EECS Department at UC Berkeley, where he is currently a full researcher in the group of Professor Brayton. Alan’s research interests are in developing computationally efficient methods for synthesis and verification.

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旅遊看世界 林玫君社群企劃 2016-03-14 13:30 BL113
旅遊看世界 演講者:林玫君社群企劃|雄獅XinMedia欣傳媒
時間:Date:2016-03-14|TIme:13:30
地點:BL113
主辦單位:電子所
協辦單位:
聯絡人:魏小姐
聯絡電話:
演講內容:
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群聯電子的創業經驗-為自己爭氣 潘建成董事長 2016-03-14 16:30 明達231
群聯電子的創業經驗-為自己爭氣 演講者:潘建成董事長|群聯電子股份有限公司
時間:Date:2016-03-14|TIme:16:30
地點:明達231
主辦單位:ICS組
協辦單位:電子所
聯絡人:林宗賢教授
聯絡電話:
演講內容:
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Ranking verification counterexamples: An invariant guided approach Ansuman BanerjeeProfessor 2016-03-07 15:30 112 BL
Ranking verification counterexamples: An invariant guided approach 演講者:Ansuman BanerjeeProfessor| Indian Statistical Institute, Kolkata, India
時間:Date:2016-03-07|TIme:15:30
地點:112 BL
主辦單位:臺大電子所
協辦單位:清大資工系
聯絡人:江介宏
聯絡電話:(02)33663685
演講內容:
Abstract:
Unit testing and verification constitute an important step in the validation life cycle of large and complex multi-component designs. Many unit validation methods often suffer from the problem of false negatives, when they analyze a component in isolation and look for errors. It often turns out that some of the reported unit failures are infeasible, i.e. the valuations of the component input parameters that trigger the failure scenarios, though feasible on the unit in isolation, cannot occur in practice considering the integrated design, in which the unit-under-test is instantiated. In this work, we consider this problem in the context of a multi-component RTL design, with a set of unit failures reported on a specific unit. We present an automated two-stage failure scenario classification and prioritization strategy that can filter out false negatives and cluster them accordingly. The use of classical AI and program analysis techniques in conjunction with formal verification helps in developing new frameworks for reasoning and deduction, which appear promising for a wide variety of problems. In particular, we discuss the results of using this technique in the context of a few RTL benchmarks.
 
Brief Bio:
Ansuman Banerjee is currently serving as an Associate Professor at the Advanced Computing and Microelectronics Unit, Indian Statistical Institute Kolkata. His research interests include design automation for embedded systems, hardware-software verification, VLSI CAD, and automata theory. Ansuman received his Ph.D. from IIT Kharagpur. Prior to joining ISI, he served as a post-doctoral researcher in the Computer Science department at National University of Singapore, and worked for Interra Systems India Pvt. Ltd., where he worked as part of the synthesis and verification team.
 
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中年阿伯的太空夢與實踐 吳宗信教授 2016-03-07 16:30 明達館 231室
中年阿伯的太空夢與實踐 演講者:吳宗信教授|交通大學機械系
時間:Date:2016-03-07|TIme:16:30
地點:明達館 231室
主辦單位:ICS組
協辦單位:電子所
聯絡人:林宗賢教授
聯絡電話:
演講內容:
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我的學思歷程 吳肇欣助理教授 2016-03-07 13:30 BL113
我的學思歷程 演講者:吳肇欣助理教授|電子所/光電所/電機系
時間:Date:2016-03-07|TIme:13:30
地點:BL113
主辦單位:電子所
協辦單位:
聯絡人:魏文儀小姐
聯絡電話:33663530
演講內容:
附加檔案:
Design and Implementation of Efficient Logic Synthesis Agorithms Victor KravetsDr. 2016-02-25 11:00 141 EE2
Design and Implementation of Efficient Logic Synthesis Agorithms 演講者:Victor KravetsDr.|IBM T.J. Watson Research Center
時間:Date:2016-02-25|TIme:11:00
地點:141 EE2
主辦單位:臺大電子所
協辦單位:臺大電機系
聯絡人:江介宏
聯絡電話:33663685
演講內容:
Abstract:
During the past two decades semiconductor industry had undergone impressive changes, offering dramatic performance benefits to the manufactured chips. Much of these improvements where facilitated by automation tools that capture physical domain characteristics of the design process. However, many automation steps at the logic abstraction level continue to be open problems. Their efficiency and quality of produced results pose important challenges in improving the overall design automation flow in semiconductor chips. To address these challenges we re-visit some of the important problems in logic synthesis. We examine how leveraging new compute powers, engineering approach to implementing algorithms, and knowledge of a chip design process can improve the quality of logic synthesis.
 
Bio:
Dr. Victor Kravets is Research Staff Member at the IBM T.J. Watson Research Center. He joined IBM in 2001, after receiving the Ph.D. degree in computer science and engineering from University of Michigan in 2001. He received the B.A. degree in computer science from Williams College. His main interests are in synthesis and   optimization of high performance designs. He was awarded with the outstanding technical achievements in IBM for contributions to the processor design closure (2007), and to the incremental synthesis and engineering change in server processors (2013).
 
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A Career Towards The Future of Computing Technologies 賴吉昌先生 2016-01-19 10:00 電機二館141教室
A Career Towards The Future of Computing Technologies 演講者:賴吉昌先生|ARM安謀國際科技股份有限公司
時間:Date:2016-01-19|TIme:10:00
地點:電機二館141教室
主辦單位:臺大電子所
協辦單位:臺大SOC中心
聯絡人:邱小姐
聯絡電話:
演講內容:
演講主題:A Career Towards The Future of Computing Technologies
演講者:賴吉昌先生/ARM安謀國際科技股份有限公司
演講時間:2016.1.19星期二上午10:00~12:00
演講地點:電機二館141室
 
演講大綱:
There are many good reasons ARM comes to Taiwan building a CPU design center, and one of them is really the strong demands of computing technologies. When many people envisioning future applications for improving our daily life, ARM always takes a further step profiling the underneath computing complexities and setting us a challenge goal to conquer them with advancement of technologies. The vision, the challenge, and the talents we are looking for are to be shared through this presentation.
 
講者介紹:
        賴吉昌先生1990年畢業於國立交通大學控制工程研究所,目前服務於ARM安謀國際科技股份有限公司,負責籌建並領導新竹設計中心技術團隊,開發新世代CPU智財產品。2005年賴先生自美返台參與創建晶心科技公司,並於多年後加入聯發科技技術長辦公室幕僚團隊。期間致力於建立新技術團隊,落實先進軟硬體智財架構設計技術平台,主導前瞻技術策略研究規劃,並在Linaro、OIC等國際性組織領導跨公司合作。稍早旅居美國時,賴先生專精於計算機結構,資料暨運算安全架構,以及設計驗證等先端核心技術,經歷數家新創團隊建制,曾負責微處理器、MODEM、MCU IP、網路安全等相關產品開發。
 
主辦單位:臺大電子所/臺大SOC中心
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SoC design trends for smartphone and IoT 梁伯嵩博士 2016-01-06 10:00 台大電機二館229室
SoC design trends for smartphone and IoT 演講者:梁伯嵩博士|聯發科技
時間:Date:2016-01-06|TIme:10:00
地點:台大電機二館229室
主辦單位:國立台灣大學電子研究所/ 教育部智慧電子整合性人才培育計畫
協辦單位:臺大系統晶片中心NTUSoCCenter
聯絡人:邱小姐
聯絡電話:33663718
演講內容:
Title: SoC design trends for smartphone and IoT 
 
時間地點:2016.1.6星期三上午10:00~12:00, 電機二館229室
 
Speaker:梁伯嵩 博士  Bor-Sung Liang, Ph.D (聯發科技)
 
Bio:
梁伯嵩博士 於2002 年獲得 國立交通大學電子研究所 博士學位,並於2013 年畢業於 國立台灣大學管理學院EMBA 商學組。現服務於 聯發科技 技術長辦公室 ,擔任技術副處長。曾於凌陽科技擔任技術開發處處長,負責自主架構處理器開發;並曾擔任凌陽核心科技副總經理,負責新竹科學園區新創IC公司設立與產品研發。
 
梁博士在技術研發上獲得許多獎項,包含 《中華民國十大傑出青年》(科技發展類) 、經濟部技術處 《產業科技發展獎 傑出青年創新獎》、中華民國資訊月《傑出資訊人才》以及 中華民國資訊學會/ ACM台灣台北分會的《李國鼎青年研究獎》等多項獎項的肯定。此外,梁博士也為多項發明專利之主要發明人,更三度獲得 經濟部智慧財產局《國家發明創作獎》之發明獎(一金二銀) 。
 
主辦單位:國立台灣大學電子研究所NTUGIEE/教育部智慧電子整合性人才培育計畫
協辦單位:臺大系統晶片中心NTUSoCCenter
 
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From Silicon to Software:Semiconductor Industry - What Next? Robert LiCountry Manager 2015-12-30 10:00 EE2-105
From Silicon to Software:Semiconductor Industry - What Next? 演講者: Robert LiCountry Manager|Synopsys Taiwan
時間:Date:2015-12-30|TIme:10:00
地點:EE2-105
主辦單位:NTU GIEE
協辦單位:NTU SoC Center
聯絡人:Susan Chiou
聯絡電話:
演講內容:
Title: From Silicon to Software:Semiconductor Industry - What Next?
Lecturer: Dr. Robert Li, Country Manager, Synopsys Taiwan
Time: 2015/12/30 (Wed) 10:00am-12:00pm
Location: EEII-229
 
Abstract:
 
Part I: What Next –
IoT. With the continuum of Moore Law for 50 years, the semiconductor technology has driven the various applications from computation, to mobile communications/networking, to software, WWW/social media/Internet to “Smart everything”. In this talk, Dr. Robert Li will focus at the “Technology+ Economics = Techonomic” trend, particularly, the different phases of IC design, namely, from Silicon to Software. The different stages include: (I) implementation, (II) Verification, (III) IP reuse, (IV) Hardware/Software co-design, and (V) Software quality/security.
 
Part II
Semi Industry Market Landscape –from WWàTaiwanàChina. Where we are and What to do next? In this part, Dr. Li will share the current worldwide Semi market status, on-going merger/acquisition, then, Taiwan semi industry eco-system and the newly raised China semi/IC design industry. Opportunities and challenges will be discussed. Some suggestions will be share in facing the China “red supply chain”: What we can do next ?
附加檔案:
SEMulator3D Applications 黃仕澔技術處長 2015-12-23 10:30 電機二館141
SEMulator3D Applications 演講者:黃仕澔技術處長|美商科文特股份有限公司
時間:Date:2015-12-23|TIme:10:30
地點:電機二館141
主辦單位:劉致為教授
協辦單位:電子所
聯絡人:胡小姐
聯絡電話:33663700#421
演講內容:
講題:SEMulator3D Applications
時間:2015年12月23日星期三,上午10:30~11:30
地點:電機二館141
講者:黃仕澔 技術處長/美商科文特股份有限公司
 
Abstract
SEMulator3D® is a powerful 3D semiconductor and process modeling platform that offers wide ranging technology development capabilities. Based on highly efficient physics-driven voxel modeling technology, SEMulator3D has a unique ability to model complete process flows.
Using unique physics-driven 3D modeling technology, the SEMulator3D modeling engine can model a wide variety of unit process steps. Each process step requires only a few geometric and physical input parameters that are easy to understand and calibrate. Just as in an actual fab, upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity, etc.) interact with each other and design data in a complex way to impact the final device structure.
 
 
Biography
Dr. Shih Hao Huang, is the technical leader Director from Coventor. He is supporting SEMulator3D for all Semiconductor Foundry in Asia-Pac. SEMulator3D is virtual fabrication 3D process modeling solution for novel and advanced manufacturing processing. His most recent position is Sr. Application Engineer of Synopsys TCAD.
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Progress in CIGSSe solar cells 程子桓CEO 2015-10-24 11:00 電二141
Progress in CIGSSe solar cells 演講者:程子桓CEO|立創光電
時間:Date:2015-10-24|TIme:11:00
地點:電二141
主辦單位:劉致為教授
協辦單位:電子所
聯絡人:胡小姐
聯絡電話:33663700#421
演講內容:
講題:Progress in CIGSSe solar cells
時間:2015年10月24日 星期六,上午11:00~12:00
地點:電機二館141
講者:程子桓
 
Abstract
·  Introduction
·  High efficiency CIGSSe solar cell
oOptical engineering 
oElectrical engineering
·  Reliability issue 
 
 
Biography
立創光電    CEO    Since 2015
台積太陽能 經理   2012~2014
台大光電所 博士   2011講題:Progress in CIGSSe solar cells
時間:2015年10月24日 星期六,上午11:00~12:00
地點:電機二館141
講者:程子桓
附加檔案:
MicroTec for Windows: Semiconductor Process and Device Simulator Michael S. ObrechtDirector of Research 2015-10-08 16:00 電二177
MicroTec for Windows: Semiconductor Process and Device Simulator 演講者:Michael S. ObrechtDirector of Research|Siborg Systems Inc, Ontario, Canada
時間:Date:2015-10-08|TIme:16:00
地點:電二177
主辦單位:電子所
協辦單位:
聯絡人:劉致為教授
聯絡電話:
演講內容:
講題:MicroTec for Windows: Semiconductor Process and Device Simulator
時間:2015年10月8日 星期四,下午4:00~5:00
地點:電機二館144
講者:Michael S. Obrecht, Ph.D.
Director of Research, Siborg Systems Inc, Ontario, Canada                
 
Abstract
Increasing performance of IBM PCs encourages the development of software tools that can be used for 2D/3D modeling of semiconductor devices and processes on a PC. Some years ago a few efficient programs of this kind were developed which have been integrated together into a package named MicroTec. The basis of these tools is a new unique numerical algorithm, based on generalized decoupled method used in contrast to conventional Newton method.
 
MicroTec allows 2D silicon process modeling including implantation, diffusion, epitaxy and oxidation and 2D steady-state semiconductor device simulation including MOSFET, SOI-MOSFET, DMOS, JFET, BJT, IGBT, Schottky devices etc. Although MicroTec is simplified compared to other available commercial simulators, it nevertheless is a very powerful modeling tool used for industrial semiconductor process/device design. In many instances MicroTec outperforms existing commercial tools and it is remarkably robust and easy-to-use.
 
Since its first commercial release in early 90's MicroTec semiconductor device simulator was used for education and research by 130+ Universities in more than 30 countries. The list includes leading academic institutions, such as University of California at Berkeley, University of Waterloo, Waseda University, Tokyo Institute of Technology, etc. The software was designed as a perfect supplement to any book on semiconductor devices or processes. It allows students to virtually make their own devices using a realistic process flow and test their performance. A limited capability version of this program was published by John Wiley & Sons as a supplement to Ton Mouthaan's book Semiconductors Devices Explained in 2000.
 
Being simplified compared to its semiconductor TCAD rivals, MicroTec was nevertheless used by more than 30 semiconductor companies including leading semiconductor manufacturers such as Hitachi, NTT, Matsushita, National Semiconductor, General Electric, Texas Instruments and Integrated Device Technology. In many cases MicroTec outperforms most of the commercial TCAD tools and it is particularly efficient for computationally extensive simulations arising in modeling of power semiconductor devices with large dimensions. MicroTec is also very useful for devices made of SiC, GaN and other materials with a wide bandgap, in particular it had been used for a few years at Cree Research for SiC device simulation. In the last five-six years MicroTec has become a choice simulator for Solar Cells.
 
 
Biography
Feb 1994–present
Director
Siborg Systems Inc · Research and Development Canada
Dec 1991–Jan 2002
Research Associate Professor
University of Waterloo · Department of Electrical & Computer Engineering · VLSI, Integrated Camera Canada · Waterloo
Sep 1975–Oct 1996
Senior Researcher
Khristianovich Institute of Theoretical and Applied Mechanics · Computational Physics Laboratory
Russia · Novosibirsk
EDUCATION
Sep 1970–Nov 1979
Novosibirsk State University
Nuclear Physics · Ph.D.
Russia · Novosibirsk
OTHER
Languages English, Russian
Scientific Societies IEEE
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Temporal Logic Modeling of Dynamical Behaviors: First-Order Patterns and Solvers Francois Fages, Director 2015-07-15 10:30 博理114
Temporal Logic Modeling of Dynamical Behaviors: First-Order Patterns and Solvers 演講者:Francois Fages, Director|INRIA, France
時間:Date:2015-07-15|TIme:10:30
地點:博理114
主辦單位:臺大電子所
協辦單位:臺灣大學與中央研究院合辦基因體與系統生物學學位學程
聯絡人:江介宏
聯絡電話:(02)33663685
演講內容:
Abstract:
In the beginning of computational systems biology in 2002, propositional temporal logic was soon proposed by computer scientists to formalize the Boolean properties of the behavior of biochemical reaction systems or gene regulatory networks. In this approach, it is possible to evaluate qualitatively what may or must happen in interaction networks of large size (e.g. of one thousand reactions and species), and to compute initial conditions (i.e. design biological experiments) to exhibit particular behaviors. This can be achieved by using the powerful model-checking tools designed for circuit and program verification. Generalizing these techniques to quantitative models can be done in two ways: either by discretizing the different regimes of the dynamics in piecewise linear or affine models, or by discretizing the numerical simulations and taking a first-order version of temporal logic with constraints on concentrations, as query language for the numerical traces. In this talk we present methods for the second approach. We illustrate their power for estimating parameters in high dimension (up to 100), and calibrating quantitative models with respect to experimental data. We describe useful patterns of first-order temporal logic formulae to facilitate their use by the modelers, present efficient solvers dedicated to them, and illustrate their use to design and measure the robustness of a synthetic biomolecular switch.
 
Bio:
François Fages is Research Director (DR1) at Inria where he leads the Lifeware group and coordinates the development of the BIOCHAM modeling software for systems biology (http://lifeware.inria.fr/biocham). In 1983, he passed his Doctorate Thesis on unification theory at age 23, and got a research position at CNRS, Ecole Normale Supérieure, where he worked on the theory and practice of rule-based and constraint logic programming, with also part-time assistant professorship at Ecole Polytechnique (1985-98) and part-time consultancy at Thomson/Thales group (1985-96).  In 1999 he joined Inria and got interested in computational systems biology where he has published 47 articles, including MolSysBiol, Bioinformatics, TCS. He leads the Master course on “Computational methods for systems and synthetic biology” in Paris. He has coordinated and participated in several European and National collaborative projects. His group composed of Grégory Batt (CR1) and Sylvain Soliman (CR1) as permanent researchers collaborates with biologists on challenging questions in cell signaling, cell cycle regulation and control of gene expression. In 2014, he received the Michel Monpetit prize from the French Academy of Sciences.
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Cells as Machines: Towards Deciphering Biochemical Programs in the Cell François Fages, Director 2015-07-14 10:30 臺大生命科學館4B階梯教室
Cells as Machines: Towards Deciphering Biochemical Programs in the Cell 演講者:François Fages, Director|INRIA, France
時間:Date:2015-07-14|TIme:10:30
地點:臺大生命科學館4B階梯教室
主辦單位:臺灣大學與中央研究院合辦基因體與系統生物學學位學程
協辦單位:臺大電子所
聯絡人:江介宏
聯絡電話:(02)33663685
演講內容:
Abstract:
Systems biology aims at understanding complex biological processes in terms of their basic mechanisms at the molecular level in cells. The bet of applying computer science concepts and methods to the analysis of biochemical reaction systems in the cell, designed by natural evolution, has led to interesting challenges in computer science, and new model-based insights in cell biology. In this talk, I shall review the development over the last decade of the biochemical abstract machine (Biocham) software environment for modeling cell biology molecular reaction systems, reasoning about them at di fferent levels of abstraction, formalizing biological behaviors in temporal logic with numerical constraints, and using them to infer non-measurable kinetic parameter values, evaluate robustness, and start deciphering natural biochemical programs.
 
Bio:
François Fages is Research Director (DR1) at Inria where he leads the Lifeware group and coordinates the development of the BIOCHAM modeling software for systems biology (http://lifeware.inria.fr/biocham). In 1983, he passed his Doctorate Thesis on unification theory at age 23, and got a research position at CNRS, Ecole Normale Supérieure, where he worked on the theory and practice of rule-based and constraint logic programming, with also part-time assistant professorship at Ecole Polytechnique (1985-98) and part-time consultancy at Thomson/Thales group (1985-96).  In 1999 he joined Inria and got interested in computational systems biology where he has published 47 articles, including MolSysBiol, Bioinformatics, TCS. He leads the Master course on “Computational methods for systems and synthetic biology” in Paris. He has coordinated and participated in several European and National collaborative projects. His group composed of Grégory Batt (CR1) and Sylvain Soliman (CR1) as permanent researchers collaborates with biologists on challenging questions in cell signaling, cell cycle regulation and control of gene expression. In 2014, he received the Michel Monpetit prize from the French Academy of Sciences.
 
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Electronic properties of few-layer black phosphorus Prof. Yuanbo Zhang 2015-07-08 16:00 電機二館105
Electronic properties of few-layer black phosphorus 演講者:Prof. Yuanbo Zhang|Department of Physics, Fudan University
時間:Date:2015-07-08|TIme:16:00
地點:電機二館105
主辦單位:電子所
協辦單位:光電所/電機系
聯絡人:張小姐
聯絡電話:33663700#421
演講內容:
講題:Electronic properties of few-layer black phosphorus
時間:2015年7月8日星期三,下午4:00~6:00
地點:電機二館105
講者:Prof. Yuanbo Zhang
      Department of Physics, Fudan University
 
Abstract
We investigate the electric property of black phosphors thin flakes with thickness down to a few atomic layers. High conductance modulations up to 105and field effect mobility up to 1000 cm2/Vs at room temperature are achieved in black phosphorus field effect transistors. We show that further improvement of the mobility is possible, and black phosphorus's superior quality has recently enabled us to observe the integer quantum Hall effect in this material. Our results suggest the potential of semiconducting black phosphorus in high speed electronics/optoelectronics.
 
 
Biography
Prof. Yuanbo Zhang received his BS from Peking University in 2000 and his PhD in Physics from Columbia University in 2006. He was a Miller Research Fellow at the University of California at Berkeley from September 2006 to June 2009, a postdoc research associate at IBM Almaden Research Center from March 2010 to September 2010, and a professor of Fudan University from 2011. His main research interests are: Electronic transport in low-dimensional systems; Scanning probe techniques and their application in studying low-dimensional nanostructures. Major honors include: Charles Townes Fellowship, Columbia University (2005); Miller Fellow, University of California, Berkeley (2006); IUPAP Young Scientist Prize, International Union of Pure and Applied Physics (2010); Qiu Shi Outstanding Young Scholar Award, Qiu Shi Foundation (2013); Nishina Asia Award, Nishina Memorial Foundation, Japan (2014).
 
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Research in CMOS scaling at imec Dr. Julien Ryckaert, Manager and Senior Researcher 2015-07-02 10:00 EEII-103
Research in CMOS scaling at imec 演講者:Dr. Julien Ryckaert, Manager and Senior Researcher|Imec
時間:Date:2015-07-02|TIme:10:00
地點:EEII-103
主辦單位:電子所
協辦單位:電機系
聯絡人:劉宗德教授
聯絡電話:
演講內容:
Title: Research in CMOS scaling at imec
Speaker: Dr. Julien Ryckaert, Manager and Senior Researcher, Imec
Time: 10:00-11:00 am, July 2 (Thursday)
Place: EEII-103, NTUEE (電機二館 103室)
 
[Abstract]
This talk will present Imec as a pioneering institute in Advanced CMOS scaling research. We will discuss how imec approaches the main challenges in scaling CMOS down to 7nm technology node and beyond. This talk aims at providing a general introduction to imec research.
 
[Biography]
Julien Ryckaert received the M.Sc. degree in Electrical Engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined IMEC (Leuven, Belgium) first as an RF designer for WLAN transceivers. From 2003 on, he worked as system architect for lowpower low data rate ultra-wideband transceivers in which he completed his PhD. In 2010 he joined the process technology division of imec coordinating the design of test chips for 3D system integration and high-speed photonics interconnects. He is now managing the design enablement team for Logic Technology and is in charge of imec’s Design-Technology Co-Optimization task force.
He is member of the Asian Solid-State Circuits Conference technical program committee.
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Video Based Human Activities Monitoring 胡玉衡教授 2015-06-29 14:30 台大博理館201室
Video Based Human Activities Monitoring 演講者:胡玉衡教授|Dept. Electrical and Computer Engineering, University of Wisconsin – Madison
時間:Date:2015-06-29|TIme:14:30
地點:台大博理館201室
主辦單位:台大電子所
協辦單位:台大系統晶片中心
聯絡人:邱玉霜
聯絡電話:33663718
演講內容:
ABSTRACT
 
A video-based hand-motion detection and tracking system is developed for the purpose of automated hand activity level assessment in a factory workplace. While the basic approach follows the sequential Bayesian estimation principle, a unique verification step is proposed to validate the quality of estimates. An experimental simulated workplace assembly line workstation is developed. The proposed system shows satisfactory performance and robustness due to the novel verification step.
*collaborators of this work include Eric Chen, Xuan Wang, and Rob Radwin

Biography

Yu Hen Hu received BSEE from National Taiwan University, Taiwan ROC in 1976, and MSEE and PhD degrees from University of Southern California, Los Angeles, CA, USA in 1982.  He was in the faculty of the Electrical Engineering Department of Southern Methodist University, Dallas, Texas. Since 1987, he has been with the Department of Electrical and Computer Engineering, University of Wisconsin, Madison where he is currently a professor.
Dr.  Hu's has broad research interests ranging from design and implementation of signal processing algorithms, computer aided design and physical design of VLSI, pattern classification and machine learning algorithms, and image and signal processing in general. He has published more than 300 technical papers, edited or co-authored three books and many book chapters in these areas.
Dr. Hu has served as an associate editor for the IEEE Transaction of Acoustic, Speech, and Signal Processing, IEEE signal processing letters, European Journal of Applied signal Processing, Journal of VLSI  Signal Processing, and IEEE Multimedia magazine. He has served as the secretary and an executive committee member of the IEEE signal processing society, a board of governor of IEEE neural network council representing the signal processing society, the chair of signal processing society neural network for signal processing technical committee, and the chair of IEEE signal processing society multimedia signal processing technical committee.  He was also a steering committee member of the international conference of Multimedia and Expo on behalf of IEEE Signal processing society.
 Dr. Hu is a fellow of IEEE.  
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Using Symbolic Methods to Verify Hybrid Systems with Large Discrete State Spaces Christoph SchollProfessor 2015-06-23 11:30 225 Ming-Dar Hall
Using Symbolic Methods to Verify Hybrid Systems with Large Discrete State Spaces 演講者:Christoph SchollProfessor|University of Freiburg
時間:Date:2015-06-23|TIme:11:30
地點:225 Ming-Dar Hall
主辦單位:臺大電子所
協辦單位:臺大電機系
聯絡人:Jie-Hong Jiang
聯絡電話:(02)33663685
演講內容:
Abstract:
 
Embedded Systems which control technical systems and perform information processing pervade more and more areas of our daily life. Due to the complexity of today's embedded systems it is becoming increasingly difficult to guarantee correctness of those systems. Since the designed systems are often used in safety-critical areas, it is not acceptable to live with compromises concerning correctness and reliability. For this reason, validation methods based on simulation (which are inherently incomplete for large systems) are more and more replaced or complemented by formal verification methods.
 
A great challenge besides the verification of pure hardware and software components consists in the verification of heterogenous systems and in the verification of embedded systems in interaction with their physical environment. Hybrid Systems are well-known models for such systems. Hybrid Systems consist of interacting discrete and continuous components. They often occur in safety-critical applications like avionics (e.g. to control the landing flaps of an aircraft), railway applications (e.g. rail traffic control systems) or chemical engineering. Here continuous components are characterized by physical quantities like speed, acceleration, temperature etc. which are changing continuously according to laws of physics. Discrete components like embedded micro controllers control the continuous components by their discrete switching behaviour. Proving the correct interaction of the discrete control with its continuous environment is a main challenge in this area.
 
The Hybrid Systems considered in this talk are given by conditional assignments to discrete and continuous variables (for modeling discrete components with controllers, sensors and actors) and by a set of (simple) differential equations (for modeling the continuous environment). In contrast to standard approaches that translate such systems into flat Linear Hybrid Automata we perform verification based on symbolic representations in order to avoid exploding representation sizes observed during such a translation - especially in case of non-trivial discrete components. The representation of the huge state spaces observed during verification is done using symbolic methods as well.
 
 
Speaker's Short Bio:
 
Christoph Scholl received the Dipl.-Inform. degree (M.S.) and Dr.-Ing. (Ph.D.) degrees in computer science from University of Saarland, Germany, in 1993 and 1997, respectively.  In 2002 he received the venia legendi from University of Freiburg, Germany.
 
In 2002/2003 he was an associate professor for computer engineering  at the University of Heidelberg and in 2003 he joined the University of Freiburg as a professor in the Department of Computer Science.
 
His research interests include logic synthesis, real-time operating systems, and the verification as well of digital circuits and systems and of hybrid systems.  In this context a main focus of his work lies on the development of efficient (symbolic) data structures and algorithms.
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半導體產業的挑戰與機會 游萃蓉副總 2015-06-08 15:30 BL113
半導體產業的挑戰與機會 演講者:游萃蓉副總|聯華電子
時間:Date:2015-06-08|TIme:15:30
地點:BL113
主辦單位:奈米電子組
協辦單位:電子所
聯絡人:張小姐
聯絡電話:33663700#421
演講內容:
演講主題:半導體產業的挑戰與機會
演講者:游萃蓉副總/聯華電子(臺南)
演講時間:日期:2015-06-08     時間:下午3:30~4:30  
演講地點:博理館113 
 
公告內容:
講題:半導體產業的挑戰與機會
時間:2015年6月8日星期一,下午3:30~4:30
地點:博理館113
講者:聯華電子(臺南)  游萃蓉副總
   聯華電子  先進技術開發副總經理
   國立清華大學材料工程學系教授                 
 
Abstract
台灣半導體產業在世界上扮演舉足輕重的角色,以半導體專業製造為例,於2014 年,台積電及聯電分別躍居全世界晶圓專工之前兩名,總產值佔60%以上。然面對全世界的劇烈競爭,台灣半導體產業將如何持續保持競爭力,提供全世界行動裝置IC設計者先進製程製造平台? 而對於快速興起之物聯網(IoT) 應用,又將有何挑戰與機會?
 
 
Biography
Dr. Tri-Rung Yew is a Vice President of Advanced Technology Development at United Microelectronics Corporation (UMC) and in charge of Advanced Technology Development. She is also a professor of the Department of Materials Science and Engineering (MSE) at National Tsing-Hua  University (NTHU).
Dr. Tri-Rung Yew received her PhD degree from the Department of Materials Science and Engineering at Massachusetts Institute of Technology (MIT) in 1990. She then joined the R&D Division at UMC for the technology development of advanced modules and process integration in 1995. She has been leading 1000 R&D team members on delivering 28nm HK/MG, Poly/SiON, and 14nm/10nm FinFET technology development since 2013.
Dr. Yew is the Chairman of SEMI Taiwan IC committee. She is also a Committee member of VLSI Symposium. Her publications include 81 international journal papers and 90 conference papers covering semiconductors and nano-/bio- technologies. She holds 141 patents with 260 certificates granted. The horary awards that she received include the “Outstanding Youth Award” in 1998, “Outstanding Youth Electronic Engineer Award” in 1999, “ROC National Invention Gold Medal Award” in 2000, “Top 10 Distinguished Engineer Award in 2001” during 1998-2001, “Outstanding Teaching Award” from Engineering College of NTHU in 2007 & 2011, “Outstanding Teacher Award” from Engineering College of NTHU in 2010, and “Outstanding Teaching Award” from NTHU in 2008 & 2012.
 
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Shannon-inspired Statistical Computing Prof. Naresh R. Shanbhag 2015-06-04 14:00 電機二館105室
Shannon-inspired Statistical Computing 演講者:Prof. Naresh R. Shanbhag|UIUC
時間:Date:2015-06-04|TIme:14:00
地點:電機二館105室
主辦單位:科技部
協辦單位:臺大電子工程學研究所 交大電子工程學系
聯絡人:邱玉霜小姐
聯絡電話:
演講內容:
【演講公告】Shannon-inspired Statistical Computing
 
講者:Prof. Naresh R. Shanbhag (University of Illinois at Urbana-Champaign)
時間:2015/6/4(四) 下午2:00~4:00
地點:台大電機二館105
 
講者介紹:
Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research interests are in the design of robust and energy-efficient integrated circuits and systems for communications including VLSI architectures for error-control coding, and equalization, noise-tolerant integrated circuit design, error-resilient architectures and systems, and system-assisted mixed-signal design. Dr. Shanbhag received the 2010 Richard Newton GSRC Industrial Impact Award, became an IEEE Fellow in 2006, received the 2006 IEEE Journal of Solid-State Circuits Best Paper Award, the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society.
 
Dr. Shanbhag is serving as an Associate Editor for the IEEE Journal on Exploratory Solid-State Computation Devices and Circuits (2014-16), served as an Associate Editor for the IEEE Transaction on Circuits and Systems: Part II (97-99) and the IEEE Transactions on VLSI (99-02 and 09-11), respectively.  He was the General Chair of the 2013 IEEE Workshop on Signal Processing Systems, the General co-Chair of the 2012 IEEE International Symposium on Low-Power Design (ISLPED), the Technical Program co-Chair of the 2010 ISLPED, and served on the technical program committee of the International Solid-State Circuits Conference (ISSCC) from 2007-11. Since January 2013, he is the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a five-year multi-university center funded by DARPA and SRC under the STARnet phase of FCRP. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of Intersymbol Communications, Inc., a venture-funded fabless semiconductor start-up that provides DSP-enhanced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links. In 2007, Intersymbol Communications, Inc., was acquired by Finisar Corporation, Inc..
 
演講大綱:
Moore's Law has been the driving force behind the exponential growth in the semiconductor industry for the past five decades. Today, energy efficiency and reliability challenges in nanoscale CMOS (and beyond CMOS) processes threaten the continuation of Moore's Law. This talk will describe our work on developing a Shannon-inspired statistical information processing that seeks to address this issue by treating the problem of computing on unreliable devices and circuits as one of information transfer over an unreliable/noisy channel. Such a paradigm seeks to transform computing from its von Neumann roots in data processing to Shannon-inspired information processing. Key elements of this paradigm are the use of statistical signal processing, machine learning principles, equalization and error-control, for designing error-resilient on-chip computation, communication, storage, and mixed-signal analog front-ends. The talk will provide a historical perspective and demonstrate examples of Shannon-inspired designs of on-chip subsystems.  This talk will conclude with a brief overview of the Systems On Nanoscale Information fabriCs (SONIC) Center, a multi-university research center based at the University of Illinois at Urbana-Champaign, focused on developing a Shannon/brain-inspired foundation for information processing on CMOS and beyond CMOS nanoscale fabrics.
 
主辦單位:科技部
協辦單位:台大電子工程學研究所 交大電子工程學系
 
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Instruction Sets Want to be Free, the Case for RISC-V Prof. David Patterson 2015-06-02 10:00 博理館201會議室
Instruction Sets Want to be Free, the Case for RISC-V 演講者:Prof. David Patterson|
時間:Date:2015-06-02|TIme:10:00
地點:博理館201會議室
主辦單位:電機資訊學院與聯發科台大創新中心
協辦單位:
聯絡人:林宜箴
聯絡電話:
演講內容:
演講資訊:
             時間:10:00AM-11:15 AM
             演講人:Prof. David Patterson
             講題:Instruction Sets Want to be Free, the Case for RISC-V
             地點: 博理館201會議室
附加檔案: Download
Moore’s Law: No End in Sight yet 黃樹群經理 2015-05-25 15:30 博理113
Moore’s Law: No End in Sight yet 演講者:黃樹群經理|ASML(台北)
時間:Date:2015-05-25|TIme:15:30
地點:博理113
主辦單位:奈米電子組
協辦單位:電子所
聯絡人:張小姐
聯絡電話:33663700#421
演講內容:
講題:Moore’s Law: No End in Sight yet
時間:2015年5月25日 星期一,下午3:30~4:30
地點:博理館113
講者:ASML(台北)  黃樹群 經理
Abstract
Semiconductor industry always follows Moore’s law to reduce the cost and enrich the functionality of IC. The current lithography process has to rely on multiple patterning steps as the semiconductor device scaling down to 30nm half-pitch (HP) and below. This presents a significant cost increase as the device geometry continues to decrease as described by the Moore’s law, a doubling of device per unit area in every two years. As the leader in semiconductor lithography technology, ASML’s solutions is aiming to keep Moore’s Law to continue. This presentation will introduce ASML lithography technology development and current updates.
 
 
Biography
David Huang (黃樹群)
2012.11~Now      ASML ACE D&E D&E Application Manager        
 
2010.11~2012.9    Einnogreen Tech   Technical Director                
 
2008.11~2010.11   Established own business                                             
 
2002.3~2008.11    KLA-Tencor tsmc BU Application manager
 
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Memory Trends, Challenges and Solutions 張琮永處長 2015-05-18 15:30 BL112
Memory Trends, Challenges and Solutions 演講者:張琮永處長|台積電DTP
時間:Date:2015-05-18|TIme:15:30
地點:BL112
主辦單位:EDA組
協辦單位:電子所
聯絡人:蔡坤諭教授
聯絡電話:
演講內容:
講題:Memory Trends, Challenges and Solutions
講者:張琮永 博士 台積電 DTP 處長
引言人:張克正 博士 台積電 DTP 副處長
時間:2015年5月18日(一) 15:30~16:30
地點:博理館112教室
 
演講摘要Abstract:
Memory continues to be critical element in VLSI applications from big data to mobile to wearables and IoT. SRAM has been at the forefront of technolo-gy scaling for every process generation. As we move to sub 20nm technolo-gy, technologists and designers faces key challenges including bit cell area scaling, VDD/Vccmin scaling, leakage and dynamic power reduction, etc. In parallel, memory industry has been looking for emerging memory solutions to replace entrenched memory technologies including SRAM, DRAM and Flash. This talk will discuss the challenges and potential solutions for SRAM scaling and the memory trends in the emerging memory.
 
講者介紹Biography :
Jonathan Chang is a director leading SRAM IP development at TSMC. He is responsible for delivering SRAM compilers, custom SRAM IPs for low power, high speed applica-tions for advance technology nodes. Jonathan joined Intel Corporation, Santa Clara, CA in 1998 and since has been engaged in the design of several high-performance micro-processors with emphasis in large, high-speed, low power cache design. He was a Principal Engineer in the area of cache design in Enterprise Microprocessor Group. In 2010, Jonathan joined TSMC, Hsin-Chu, Taiwan.
Jonathan is a senior member of the IEEE and serves as a technical program committee member of Memory subcommittee for ISSCC since 2013. Jonathan also was the NAE (North America and Europe) technical program committee member of 2011 VLSI sym-posium on circuits and associate editor of IEEE Trans on VLSI. Jonathan has published 20+ technical papers in IEEE conferences or journals.
Jonathan Chang received the B.S. degree in electrical engineering from National Taiwan University, and the M.S. and Ph.D. degrees in electrical engineering from Stanford Uni-versity, Stanford, CA.
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Holistic photolithography- imaging solutions of IC patterning technology for future 邱燦賓博士 Senior Imaging Scientist 2015-05-11 15:30 博理112教室
Holistic photolithography- imaging solutions of IC patterning technology for future 演講者:邱燦賓博士 Senior Imaging Scientist|ASML
時間:Date:2015-05-11|TIme:15:30
地點:博理112教室
主辦單位:EDA組
協辦單位:電子所
聯絡人:蔡坤諭敎授
聯絡電話:
演講內容:
演講題目: Holistic photolithography- imaging solutions of IC patterning technology for future
講者:邱燦賓 博士
Senior Imaging Scientist, ASML
時間:2015年5月11日(一) 15:30~16:30
地點:博理館112教室
 
演講摘要Abstract :
Lithography is the most critical process in today’s semiconductor manufacturing technology. When IC devices keep shrinking for the future nodes according to Moore’s law, requirement of critical dimension (CD) control in printing device pat-terns becomes even more challenging. Improvement of control systems such as dose, focus, lens, or overlay control in a scanner enhances uniformity of the printed CD; however, the CD uniformity may not meet the strict requirement. ASML in-troduced a new concept, holistic lithography, intending to fulfill the tight CD con-trol requirement. The holistic lithography is based on an intelligent integration of scanner control, computational lithography, wafer fab lithography and metrology, which together extend the imaging and overlay capabilities of ASML scanners. It attempts to better maintain CD uniformity of multiple wafers/lots through multiple links among scanner, computational lithography and metrology tool. We highly ex-pect that the new concept is able to support IC patterning technology for the next decade.
The talk will cover the following topics: requirement of lithography capability, crit-ical metrics that represent lithography process quality, lithography challenges and their possible solutions, approaches to improve the lithographic metrics, concept of holistic lithography, alternative IC design styles, and EUV imaging capability.
 
講者介紹Biography :
Tsann-Bim Chiou is currently a Senior Image Scientist in the Technology Develop-ment Center at ASML. He received his PhD degree of Power Mechanics Engineer-ing from Tsinghua Univ., Hsinchu, Taiwan in 1996. After graduation, he worked in National Nano Device Laboratories, Hsinchu, Taiwan, as an associate researcher in charge of lithographic process development and support. In 2001, he joined ASML as a research engineer working on development of image quality improvement and various resolution enhancement technologies. In the period, he involved many pro-jects to help solving various imaging and overlay issues; meanwhile he also evaluat-ed various possible patterning solutions. He is now working on design rule optimi-zation and exploration of immersion ArF extensions and EUV capabilities for the future nodes. He has authored and coauthored more than 30 journal and confer-ence papers and articles.
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Advanced High-Frequency Measurement Techniques for Electrical and Biological Characterization in CMOS Jun-Chau ChienPh.D. candidate 2015-04-28 13:30 BL201
Advanced High-Frequency Measurement Techniques for Electrical and Biological Characterization in CMOS 演講者:Jun-Chau ChienPh.D. candidate|Electrical Engineering, University of California, Berkeley.
時間:Date:2015-04-28|TIme:13:30
地點:BL201
主辦單位:電子所
協辦單位:
聯絡人:吳依倩
聯絡電話:33663529
演講內容:
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IC設計流程與工作經驗分享 洪崇文部經理 2015-04-27 16:30 明達231
IC設計流程與工作經驗分享 演講者:洪崇文部經理|聯詠
時間:Date:2015-04-27|TIme:16:30
地點:明達231
主辦單位:ICS組
協辦單位:電子所
聯絡人:盧信嘉教授
聯絡電話:
演講內容:
題目: IC設計流程與工作經驗分享
演講者 部經理-Director洪崇文   聯詠
演講時間 日期2015/04-27 時間16.30
演講地點 明達231
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Do We Understand Deep Learning? 蔡雋永博士後研究員 2015-04-21 13:30 電機二館105演講廳
Do We Understand Deep Learning? 演講者:蔡雋永博士後研究員|哈佛大學
時間:Date:2015-04-21|TIme:13:30
地點:電機二館105演講廳
主辦單位:台大電子所
協辦單位:聯發科技-台大創新研究中心
聯絡人:張雅絢
聯絡電話:33663708
演講內容:
Deep neural networks have been successfully pushing the boundaries of computer vision by breaking the records of ImageNet Challenges year after year, and the representations of deep artificial neurons also have been demonstrated to be highly effective and robust for various visual recognition tasks. Nevertheless, our understanding of the properties of these networks arguably remains limited. For example, researchers started to notice and had reported that images with imperceptible distortions or being artificially generated and completely unrecognizable (i.e. adversarial examples), can in many cases easily fool deep learning algorithms. Fundamentally, we lack a comprehensive functional understanding of how these system work at a theoretical level.
In this seminar, I will first talk about our recent progress on measuring and understanding sensory representations within deep networks, which addressed two important and practical questions: (1) why deep networks are better than shallow networks, and (2) among networks of the same depth, why certain networks are better than the others. We considered the case study of face pair matching and conducted a large-scale experiment in which we examined 200 randomly generated shallow and deep networks. Our results suggest that deep representations are quantitatively better than shallow representations, and overall 71% of the variance in the performance of deep networks can be explained using our methods, both of which are confirmed for the first time using statistical tests. Time permitting, I will introduce another on-going project which aims at providing a web platform for efficiently discovering adversarial examples and potentially collecting human responses. Our preliminary results indicate that, deep networks are indeed intriguingly fragile, but at the same time, highly "creative and knowledgeable" as well. We hope this project can potentially help us better characterize deep learning algorithms and the way they agree or disagree with human vision.
 
BIO:
Chuan-Yung Tsai received his Ph.D. degree in Electronics Engineering from National Taiwan University in 2012. He is a postdoctoral researcher at Center for Brain Science, Harvard University, since 2013. His research interests include computational and theoretical neuroscience, neuromorphic engineering, computer vision, digital signal processing, VLSI design, etc.
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Emerging Non-Volatile Memory Development Worldwide Statusv 何家驊處長 2015-04-20 15:30 博理館113
Emerging Non-Volatile Memory Development Worldwide Statusv 演講者:何家驊處長|華邦電子
時間:Date:2015-04-20|TIme:15:30
地點:博理館113
主辦單位:奈米電子組
協辦單位:電子所
聯絡人:張小姐
聯絡電話:33663700#421
演講內容:
講題:Emerging Non-Volatile Memory Development Worldwide Status
時間:2015年4月20日 星期一,下午3:30~4:30
地點:博理館113
講者:華邦電子(新竹)  何家驊 處長
Abstract
Being various applications on storage class memory (SCM), several emerging memories were announced few years ago with functionality between or beyond current NAND Flash memory and DRAM/SRAM. Those memories include STT-MRAM, PRAM, and RRAM. Reliability and speed wise, STT-MRAM has potential to replace DRAM, or even L2/L3 catch memory, or embedded memory applications. But its cost is relatively higher than the others. Die-cost wise, 2D RRAM can offer potential for cost-effective EEPROM, low-density NOR Flash memory, or even embedded memory applications with faster speed. With breakthrough of 3D RRAM selector, it can furthermore offer potential for competing 3D NAND ultra high density. Those technologies are believed to mass production in near term future.
 
 
Biography
ChiaHua Ho received Ph.D. degree in department of physics from the National Taiwan University in Jan. of 2002. He now works with Winbond Electronics Corporation and is in charge of Director of New Memory Technologies Development Division. From 2001~2013, he was with MXIC (Macronix International Co. Ltd.), IBM/MXIC/Infineon alliance at T. J. Watson Lab of IBM, tsmc (Taiwan Semiconductor Manufacturing Company), and NDL (National Nano Device Laboratories). The fields he worked on include emerging non-volatile memories, such as P-RAM, R-RAM, and M-RAM, novel NAND Flash memory, and 32nm/28nm node CMOS technology, etc. So far he publishes more than 85 US granted patents, 60 Taiwan granted patents, 60 China granted patents, more than 10 IEDM and VLSI Symposium papers, more than 40 conference and journal papers, and authored textbook chapter for R-RAM as well.
 
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High-Speed IO Trends and Challenges 謝正祥副處長 2015-04-13 16:40 明達231
High-Speed IO Trends and Challenges 演講者:謝正祥副處長|台積電
時間:Date:2015-04-13|TIme:16:40
地點:明達231
主辦單位:電子所ICS組
協辦單位:
聯絡人:盧信嘉教授
聯絡電話:
演講內容:
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奈米CMOS電子設計自動化軟體的研發與奈米CMOS 電路的最佳化 喻秉鴻技術副理 2015-04-13 15:30 博理112
奈米CMOS電子設計自動化軟體的研發與奈米CMOS 電路的最佳化 演講者:喻秉鴻技術副理|台積電
時間:Date:2015-04-13|TIme:15:30
地點:博理112
主辦單位:電子所EDA組
協辦單位:TSMC-NTU Center、SOC Center
聯絡人:蔡坤諭教授
聯絡電話:
演講內容:
Speech title: 奈米CMOS電子設計自動化軟體的研發與奈米CMOS 電路的最佳化。
The English speech title: R&D of Nano-CMOS EDA Software for Nano-CMOS Circuit Optimization
 
Speaker: 台積電技術副理 喻秉鴻博士Dr. Ping-Hung Yuh
 
Abstract:
當CMOS元件進入奈米大小時,製程的複雜度越來越高,但是對效能,耗電,和time-to-market的要求並沒有放鬆。在這種情況之下,製程最佳化的完成時間點是很重要的。最佳化完成的時間點將直接影響某一世代製程的競爭力。為了達到這個目標,內部(in-house)軟體的支援是很重要的一環。內部軟體可以模擬不同的製程選項,早期測試製程對電路的影響,並提供最佳化的方向。其中,最重要的內部軟體之一是寄生電容抽取(parasitic extraction)軟體。此軟體的準確度將直接影響分析或模擬的結果,並可能導致不一樣的最佳化方向。這場演講會包含三個部分。首先是製程開發的挑戰。根據這些挑戰,內部軟體開發將扮演甚麼樣的角色。接下來是介紹寄
生電容抽取相關的技術以及它在設計流程(design flow)中的角色。最後,傳統上,寄生電容相關的效應並不是最佳化的目標。但當製程越來越複雜,且電路和製程要一起最佳化時,寄生電容相關的效應必須是最佳化的一環。
 
Bio:
喻秉鴻博士目前在新竹台積電總部設計暨技術平台部門(DTP)研發電子設計自動化(EDA)軟體,發展奈米電路寄生電路抽取(parasitic extraction)技術,以及電路最佳化(optimization)技術。他曾任職於新思科技(Synopsys)。喻秉鴻博士於2008年因為張耀文教授與楊佳玲教授的共同指導,從台大電資學院拿到博士學位。2007年至2008
年,藉由千里馬計畫的補助,他於明尼蘇達大學(university of Minnesota)擔任訪問學者。在學期間總共發表了19篇論文。他曾於2007年榮獲IEEE ICCAD Professor Margarida Jacome Memorial Award。他的數位微流體晶片(digital microfluidic biochips)的研究曾登上EE Times (title: Lab-on-chip design automation takes cue from EDA, in 2008)。
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Energy-Efficient VLSI Signal Processing for Multi-dimensional Biomedical and Communication Systems 楊家驤副教授 2015-03-30 10:30 電機二館141室
Energy-Efficient VLSI Signal Processing for Multi-dimensional Biomedical and Communication Systems 演講者:楊家驤副教授|國立交通大學電子系
時間:Date:2015-03-30|TIme:10:30
地點:電機二館141室
主辦單位:台大電子所
協辦單位:
聯絡人:邱小姐
聯絡電話:33663718
演講內容:
Energy-Efficient VLSI Signal Processing for Multi-dimensional Biomedical and Communication Systems
    時間:2015.3.30(星期一)上午10:30-12:00
   地點:台灣大學電機二館141室
   講者:楊家驤  副教授 (國立交通大學電子系)
Abstract
Due to the growing computational complexity and limited energy budget, energy-efficient VLSI signal processing for multi-dimensional signals is essential. Design optimization across algorithm, architecture, and circuit layers are addressed to minimize energy/power consumption. The methodology has been applied to complex communication and biomedical signal processing to achieve high energy efficiency. Without degradation of the energy efficiency, an ultra-low-power biosignalprocessor with dedicated accelerators has been developed. The developed processing platform is being developed for mobile 3D imaging, including LORETA (low resolution brain electromagnetic tomography) and ECGI (electrocardiographic imaging) by reversing multi-channel EEG and ECG signals, respectively. With the aid of wireless technology, potential applications of the LORETA and ECGI technologies include mobile 3D brain and heart monitoring, especially when subjects are in movement. Baseband signal processing and VLSI realization for next-generation mobile systems are also being developed for biomedical devices that require even faster data transmission.
Bio
Chia-Hsiang Yang received his B.S. and M.S. degrees from the National Taiwan University, Taiwan, in 2002 and 2004, respectively, all in Electrical Engineering. He received his Ph.D. degree from the Department of Electrical Engineering of the University of California, Los Angeles in 2010. He then joined the faculty of the Electronics Engineering Department at the National ChiaoTung University, Taiwan, where he is currently an Associate Professor. His research interests focus on energy-efficient integrated circuits and architectures for biomedical and communication signal processing.
 
Dr. Yang was a winner of the DAC/ISSCC Student Design Contest in 2010. He received the 2010-2011 Distinguished Ph.D. Dissertation in Circuits & Embedded Systems Award from the Department of Electrical Engineering, University of California, Los Angeles. In 2013, he was a co-recipient of the ISSCC Distinguished-Technical-Paper Award.
 
主辦單位: 台灣大學電子工程學研究所
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From Circuits to Cognitive Computing: Big opportunities from Hardware perspectives Dr. Gi-Joon Nam 2015-03-23 15:30 BL112
From Circuits to Cognitive Computing: Big opportunities from Hardware perspectives 演講者:Dr. Gi-Joon Nam|IBM T. J. Watson Research Center, NY
時間:Date:2015-03-23|TIme:15:30
地點:BL112
主辦單位:電子所
協辦單位:電機系
聯絡人:張耀文教授
聯絡電話:
演講內容:
Title: From Circuits to Cognitive Computing: Big opportunities from Hardware perspectives
Speaker: Dr. Gi-Joon Nam (gnam@us.ibm.com)
IBM T. J. Watson Research Center, NY
Time: 15:30-16:20, March 23, 2015 (Monday)
Place: Room112, Barry Lam Hall 
            Dept. of EE, National Taiwan University
Abstract:

Mobile and Cloud computing have been enabling cyberspace accessible to virtually everyone and transforming the daily lives of people for the better. We truly live in the world with the explosion of computing devices and data. Sensors are everywhere and the data generated from them (including mobile devices) grow at a faster rate than the rate at which processing capacity grows. The demand for higher computing capacity and intelligent processing is stronger than ever before. In this talk, I will go over the new computing paradigm, Cognitive Computing, to address this trend. Then, I'll give an overview of a few related interesting yet transformative projects that are going on in IBM research. The topics range from circuits (P/Z processors with sub-20nm technologies) to system architectures for big data applications (OpenPower project) to cognitive computing (SyNAPSE, the brain inspired Neurosynaptic chip). Then, I will conclude the talk that this is an exciting time to be a computer & electrical engineers with tremendous opportunities lying ahead.

Bio: Gi-Joon Nam received his B.S in Computer Engineering from Seoul National University and MS. and Ph.D. degrees in Computer Science and Engineering from the University of Michigan, Ann Arbor in 2001. Since then, Dr. Nam is with IBM Research organization and currently he is a Research Staff Member and Manager at the IBM T. J. Watson Research Center managing the Physical Design Department for IBM P & Z server microprocessors. Prior to this, he managed the Optimized Analytics System department in the IBM Austin Research Lab working on the workload-optimized systems for big data applications. In the past 10+ years, Dr. Nam has been involved with variety of projects in IBM such as EDA (Electronic Design Automation) software development for IBM's in-house Place&Route tools, processor designs for P & Z microprocessors, the system & memory architecture research for big data applications, cognitive computing and smart planet projects. He is a senior member of IEEE and ACM.
 
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Two Current Research Topics at Yale University: Unipolar CMOS Logic and 1-T Ferroelectric Memory Technology Prof. Tso Ping Ma 2015-03-11 10:00AM BL201
Two Current Research Topics at Yale University: Unipolar CMOS Logic and 1-T Ferroelectric Memory Technology 演講者:Prof. Tso Ping Ma|Yale University
時間:Date:2015-03-11|TIme:10:00AM
地點:BL201
主辦單位:電子所
協辦單位:電資學院
聯絡人:吳依倩
聯絡電話:
演講內容:
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Sleep Research and Me: the Past and Future Prof. Yoshihiro Urade 2015-02-10 14:00 BL114
Sleep Research and Me: the Past and Future 演講者:Prof. Yoshihiro Urade|University of Tsukuba, Japan
時間:Date:2015-02-10|TIme:14:00
地點:BL114
主辦單位:聯發科技-臺大創新研究中心
協辦單位:電子工程學研究所
聯絡人:張耀文教授
聯絡電話:
演講內容:
Title: Sleep Research and Me: the Past and Future
Speaker:  Professor Yoshihiro Urade
                  International Institute for Integrative Sleep Medicine (WPI-IIIS)
                  University of Tsukuba, Tsukuba, Japan
Time: 2-3pm, February 10, 2015 (Tuesday)
Place: Rm 114, Barry Lam Hall, Dept. of Electrical Engineering, National Taiwan University
Discussion session: 3-4pm in Rm 401-1 (inside the GIEE office), Barry Lam Hall
 
Abstract:
 
Why do we need sleep? Why do we wake up? What is the mechanisms underlying sleep?
Sleep occupies one-third of our life. Recent studies demonstrated that insufficient sleep causes various diseases, including dementia and obesity. As such, solving the mystery of sleep is more important than ever.
 
Today, I will present the results of my research, hoping that this scientific meeting will contribute to solving the mystery of sleep and promoting the welfare of human kind.
 
I have been working on sleep research since 1981. My research for 30 years can be divided into four parts.
 
First, we identified endogenous sleep-promoting factors, such as prostaglandin D2 (PGD2) and adenosine. We created various mouse models to show that these two factors are indeed physiologically relevant to the regulation of sleep in mammals.
 
Second, we discovered several sleep-promoting substances from foods and herbs.
In the last ten years, we developed a screening system to determine the quality and the quantity of sleep in mice by measuring their electroencephalogram (EEG), so-called brain wave. Utilizing this sleep bioassay system, we screened more than 300 different kinds of components extracted from various foods, herbs and traditional Chinese medicines. Based on these results, we received a huge grant from the Japanese government to further promote this project. Also, we are currently collaborating with many Japanese biomedical companies to develop new sleep-inducing food products and supplements, as well as a new animal model of micro-miniature pigs, which have similar sleep patterns to humans.
 
Third, we developed a novel technique for home-monitoring daily sleep patterns in humans. Currently, our portable EEG device is used at many sleep research centers, including the Japanese Space Center and the Japanese Antarctica Research Center, to measure sleep of astronauts on the International Space Station (ISS) and scientists in the Wintering Base, respectively.
 
We have been working on PGD2, which plays critical roles in sleep regulation.  Interestingly, however, we also discovered that PGD2 is involved in the pathogenesis of muscular dystrophy. We found that there are two distinct types of PGD2 synthase: the L type (L-PGDS) and the H type (H-PGDS). We developed a potent H-PGDS inhibitor and found that administration of H-PGDS inhibitor improves the clinical course of  muscular dystrophy. We brought this enzyme to the ISS to crystalize it under micro gravity condition. Through the development of these technologies, we give encouragement and hope to muscular dystrophy patients and their families.
 
I hope that in the near future, the portable EEG device can be used by the general population to monitor their daily sleep at home, similar to the thermometer used in most households to measure body-temperature.  If everyone can understand their own daily sleep conditions and manage their sleep by themselves, the future of mankind will certainly be more productive.
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未來5G相關Topic及mmWave 量測 台灣是德科技 2015-01-27 10:00 電機二館 103 會議室
未來5G相關Topic及mmWave 量測 演講者:台灣是德科技|
時間:Date:2015-01-27|TIme:10:00
地點:電機二館 103 會議室
主辦單位:台灣是德科技
協辦單位:台大電子所、電機系
聯絡人:周泓廷
聯絡電話:
演講內容:
本月1/27日(星期二) 台灣是德科技(原安捷倫Agilent) 將會在電子所舉辦一場〝未來5G相關Topic及mmWave 量測〞的小型Seminar。
(PS.本活動屆時亦免費提供午膳便當~!!)
 
時程
研討會日期
2015/01/27 (二)
研討會報到時間
上午9:40 ~ 10:00
研討會時間
上午10:00 ~ 下午4:00
研討會地點
電機二館103 會議室
台灣是德科技相關訊息
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「金矽獎攻克寶典?」 李世光特聘教授 2014-12-29 10:10 電機二館141室
「金矽獎攻克寶典?」 演講者:李世光特聘教授|台灣大學應用力學研究所
時間:Date:2014-12-29|TIme:10:10
地點:電機二館141室
主辦單位:電子所
協辦單位:旺宏金矽獎
聯絡人:吳依倩
聯絡電話:
演講內容:
【演講資訊】
講者:李世光 特聘教授(台灣大學應用力學研究所) 
題目:「金矽獎攻克寶典?」
日期:103年12月29日上午10:10-11:30
地點:電機二館141室
 
最來有高達近百位的學者、專家參與旺宏金矽獎的評審工作。這些專家的工作裡,有很大一部分就是在聽取各種簡報,判讀資訊,然後做出一個又一個的決定,帶領組織往成功的目標邁進。如何讓自己的作品獲得這些專家青睞,脫穎而出,不僅是提高獲獎機會的關鍵,也是在職場上(不管你/妳未來選擇投身研究,或到業界工作)一生受用的技巧。旺宏金矽獎十分榮幸能在第13、14屆時,邀請到經歷豐富的李世光教授曾參與評審工作,並且在這一屆邀請李老師來談談他從競賽裡看到的學生作品,提點準備的方法。百忙之中抽空的寶貴分享,請大家千萬不要錯過囉!
 
請先上網登記報名:http://goo.gl/NnH2wQ
 
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參加NASA載人火星探索計畫任務規劃的經驗 葛廣漢董事長 2014-12-29 15:30 BL112
參加NASA載人火星探索計畫任務規劃的經驗 演講者:葛廣漢董事長|廣碩系統
時間:Date:2014-12-29|TIme:15:30
地點:BL112
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
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IC Design Challenges Dr. Koan Huang處長 2014-12-22 15:30 博理112
IC Design Challenges 演講者:Dr. Koan Huang處長|MediaTek
時間:Date:2014-12-22|TIme:15:30
地點:博理112
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
講者: 聯發科技黃坤進處長(Dr. Koan Huang)
講題: IC Design Challenges
時間: 2014/12/22 15:30~16:20
地點: BL-112
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How to Make a SIGGRAPH Paper While Having All the Fun Prof. Li-Yi We 2014-12-15 15:30 博理館112室
How to Make a SIGGRAPH Paper While Having All the Fun 演講者:Prof. Li-Yi We|The University of Hong Kong
時間:Date:2014-12-15|TIme:15:30
地點:博理館112室
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
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Understanding and Coping with Variabilities and Defects in Fabrication, Biochemistry, and Sensing for Microfluidic Biochips Prof. Krishnendu ChakrabartyProfessor 2014-12-08 15:30 博理112
Understanding and Coping with Variabilities and Defects in Fabrication, Biochemistry, and Sensing for Microfluidic Biochips 演講者:Prof. Krishnendu ChakrabartyProfessor|Duke University
時間:Date:2014-12-08|TIme:15:30
地點:博理112
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
Title: Understanding and Coping with Variabilities and Defects in Fabrication, Biochemistry, and Sensing for Microfluidic Biochips
Speaker: Prof. Krishnendu Chakrabarty
Duke University
Time: 3:30-4:20pm, December 8, 2014 (Monday)
Place: BL-112
Dept. of Electrical Engineering
National Taiwan University
 
Abstract:  
Recent advances in microfluidics have led to the emergence of biochemistry-on-a-chip as a new paradigm in clinical diagnostics and biomolecular recognition. However, potential roadblocks in the deployment of microfluidic biochips are variabilities, defects, and the lack of efficient test techniques to screen defective devices before they are used for biochemical analysis. Defective chips lead to the repetition of experiments, which is undesirable due to high reagent cost and limited availability of samples. This lecture will describe the causes underlying variabilites, and techniques for coping with them through advances in automated testing. The proposed test techniques are based on behavioral abstractions of actual physical defects. The speaker will describe a comprehensive experimental setup and results obtained using fabricated chips, as well as a case study of sensor-driven cyberphysical error recovery.
 
Biography:
 
Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor in the Department of Electrical and Computer Engineering at Duke University. Prof. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, and 10 best papers awards at IEEE conferences.
 
Prof. Chakrabarty’s current research projects include: testing and design-for-testability of integrated circuits; digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure. He has authored 15 books on these topics (with one more book in press), published nearly 500 papers in journals and refereed conference proceedings, given over 30 tutorials at top conferences, and presented over 210 invited, keynote, and plenary talks. Prof. Chakrabarty is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He was a 2009 Invitational Fellow of the Japan Society for the Promotion of Science (JSPS). He is a recipient of the 2008 Duke University Graduate School Dean’s Award for excellence in mentoring, and the 2010 Capers and Marion McDonald Award for Excellence in Mentoring and Advising, Pratt School of Engineering, Duke University. He served as a Distinguished Visitor of the IEEE Computer Society during 2005-2007 and 2010-2012, and as a Distinguished Lecturer of the IEEE Circuits and Systems Society during 2006-2007 and 2012-2013. Currently he serves as an ACM Distinguished Speaker.
 
Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012. Currently he serves as Editor-in-Chief of ACM Journal on Emerging Technologies in Computing Systems. He is also an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on Computers, ,and IEEE Transactions on Biomedical Circuits and Systems. He serves as an Editor of the Journal of Electronic Testing: Theory and Applications (JETTA).
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從2025大趨勢看未來發展 高雅玲資深產業分析師/組長 2014-11-17 13:30 BL113
從2025大趨勢看未來發展 演講者:高雅玲資深產業分析師/組長|資策會產研所
時間:Date:2014-11-17|TIme:13:30
地點:BL113
主辦單位:電子所
協辦單位:
聯絡人:魏文儀小姐
聯絡電話:
演講內容:
講者:資策會產研所-高雅玲資深產業分析師/組長
講題:從2025大趨勢看未來發展
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Data Model Analysis and Verification Prof. Tevfik Bultan 2014-11-14 11:00 BL103
Data Model Analysis and Verification 演講者:Prof. Tevfik Bultan|University of California at Santa Barbara
時間:Date:2014-11-14|TIme:11:00
地點:BL103
主辦單位:電機系
協辦單位:
聯絡人:王凡教授
聯絡電話:
演講內容:
Title: Data Model Analysis and Verification
Speaker: Tevfik Bultan, University of California at Santa Barbara
Room: 博理館103
Time: 11am, Friday, November 14, 2014.
 
The growing influence of web applications in every aspect of society makes their dependability an immense concern. One positive advancement in web application development has been the adoption of the Model-View-Controller (MVC) pattern. Many popular web application development frameworks such as Ruby on Rails, Zend for PHP, CakePHP, Django for Python, and Spring for J2EE are based on the MVC pattern. A fundamental building block of web the MVC pattern is the data model, which specifies the object classes and the relations among them. The MVC pattern facilitates the separation of the data model (Model) from the user interface logic (View) and the control flow logic (Controller). The modularity and separation of concerns principles imposed by the MVC pattern provide opportunities for developing customized verification and analysis techniques. 
 
MVC-based frameworks use an object-relational mapping (ORM) to map the data representation of the web application to the back-end database. We developed an approach for automated verification of data models that 1) extracts a formal data model from the given ORM specification, 2) converts verification queries about the data model to queries about the satisfiability of logic formulas, and 3) uses a decision procedure or theorem prover to check the satisfiability of the resulting formulas. We implemented this approach and applied it to open-source Rails applications, discovering data model errors in existing applications and demonstrating the effectiveness of our approach.
 
 
SPEAKER BIO:
 
Tevfik Bultan is a Professor in the Department of Computer Science at the University of California, Santa Barbara (UCSB). His current research interests are in dependability of web software and services, automated verification, string analysis, and data model specification and analysis.
Dr. Bultan co-chaired the program committees of the 9th International Symposium on Automated Technology for Verification and Analysis (ATVA 2011), the 20th International Symposium on the Foundations of Software Engineering (FSE 2012), and the 28th IEEE/ACM International Conference on Automated Software Engineering (ASE 2013).  Dr. Bultan was a keynote speaker at the 19th International Conference on Concurrency Theory (CONCUR 2008), the 6th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2008), the 9th International Symposium on Formal Aspects of Component Software (FACS 2012), and the 2013 IFIP Joint International Conference on Formal Techniques for Distributed Systems (33rd FORTE / 15th FMOODS).
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VLSI EDA 2.0: Life past Moore as we await the Nano Savior Dr. Sani Nassif 2014-11-10 15:30 博理112
VLSI EDA 2.0: Life past Moore as we await the Nano Savior 演講者:Dr. Sani Nassif|IBM
時間:Date:2014-11-10|TIme:15:30
地點:博理112
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
Dr. Sani Nassif
President, IEEE Council on EDA
Fellow, IEEE
CEO, Radyalis, Texas, USA
Time: 15:30-16:20, November 10, 2014 (Monday)
Place: Room112, Barry Lam Hall, Dept. of EE
National Taiwan University
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[Workshop on Advanced VLSI Design Techniques] Completely Completion Detection Asynchronous Circuit Designs for Low Voltage Autonomous Control Prof. Makoto IKEDA 2014-11-07 10:00 博理館201室
[Workshop on Advanced VLSI Design Techniques] Completely Completion Detection Asynchronous Circuit Designs for Low Voltage Autonomous Control 演講者:Prof. Makoto IKEDA|The University of Tokyo
時間:Date:2014-11-07|TIme:10:00
地點:博理館201室
主辦單位:電子所
協辦單位:台大系統晶片中心, IEEE SSCS Taipei Chapter
聯絡人:邱玉霜
聯絡電話:
演講內容:
【演講公告】Workshop on Advanced VLSI Design Techniques
 
時間:2014/11/7()
地點:台大博理館201
 
講題一:Completely Completion Detection Asynchronous Circuit Designs for Low Voltage Autonomous Control
講者一:Prof. Makoto IKEDA (The University of Tokyo)
講者介紹:
Makoto Ikedareceived the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now professor at the department of electrical engineering and information systems. At the same time he has been involving the activities of VDEC(VLSI Design and Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia. He worked for asynchronous circuits design, smart image sensor for 3-D range finding, and time-domain circuits for associate memories. He has published more than 230 technical publications, including 10 invited papers, and 7 books/chapters. He serves international conferences as TPC members, Organizing committee members as well as Steering committee members, including, ISSCC, VLSI Symposium, A-SSCC, ICCAD, ICFPT, ISQED.
 
主辦單位:台灣大學電子所
協辦單位:台大系統晶片中心 IEEE SSC, Taipei Chapter
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[Workshop on Advanced VLSI Design Techniques]Technology and Experience to realize integration of control and network Sugako Otani 2014-11-07 10:00 博理館201室
[Workshop on Advanced VLSI Design Techniques]Technology and Experience to realize integration of control and network 演講者:Sugako Otani|Renesas Electronics Corporation
時間:Date:2014-11-07|TIme:10:00
地點:博理館201室
主辦單位:電子所
協辦單位:台大系統晶片中心 IEEE SSCS Taipei Chapter
聯絡人:邱玉霜
聯絡電話:
演講內容:
【演講公告】Workshop on Advanced VLSI Design Techniques
 
時間:2014/11/7()
地點:台大博理館201
 
講題二:Technology and Experience to realize integration of control and network
講者二:Sugako Otani  (Renesas Electronics Corporation)
講者介紹:
Sugako Otani is a processor architect of RX at Renesas Electronics Corporation, where she is responsible for the processor. From 2005 to 2006, she was a Visiting Scholar at Stanford University. Her research interests include microprocessor architectures and networking. Otani has an MS in physics from Waseda University, Japan. She is currently serving for A-SSCC TPC.
 
 
主辦單位:台灣大學電子所
協辦單位:台大系統晶片中心 IEEE SSC, Taipei Chapter
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Thermal-aware 3D Network-on-Chip (NoC) Designs Dr. Kun-Chih ChenResearcher 2014-11-03 15:30 博理112
Thermal-aware 3D Network-on-Chip (NoC) Designs 演講者:Dr. Kun-Chih ChenResearcher|INTEL-NTU Research Center
時間:Date:2014-11-03|TIme:15:30
地點:博理112
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
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Introduction to Power Management IC & Its Challenge on TFT-LCD Panels 吳清逸副處長 2014-11-03 13:30 博理館113室
Introduction to Power Management IC & Its Challenge on TFT-LCD Panels 演講者:吳清逸副處長|奇景光電
時間:Date:2014-11-03|TIme:13:30
地點:博理館113室
主辦單位:電子所
協辦單位:SOC中心
聯絡人:魏文儀
聯絡電話:
演講內容:
電子所將於11/3(一)邀請奇景光電 吳清逸副處長
至本所演講,演講資訊如下,歡迎踴躍參加。
 
講者:奇景光電 吳清逸副處長
講題:Introduction to Power Management IC & Its Challenge on TFT-LCD Panels
日期:11月3日(一)
時間:13:30-15:00
地點:博理館113室
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IC Design Challenges and Opportunities - A New Chapter of Bridging the Miniaturization, the Tools, and the Applications 李憲信副處長 2014-10-27 15:30 BL112
IC Design Challenges and Opportunities - A New Chapter of Bridging the Miniaturization, the Tools, and the Applications 演講者:李憲信副處長|台積電設計法則暨套件發展處
時間:Date:2014-10-27|TIme:15:30
地點:BL112
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
10/27 15:30~16:20 BL-112
 
題目:IC Design Challenges and Opportunities - A New Chapter of Bridging the Miniaturization, the Tools, and the Applications
講者:李憲信博士
職稱:台積電設計法則暨套件發展處  副處長
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Simulation and mitigation approaches for soft errors at advanced technology nodes Prof. Bharat BhuvaProfessor 2014-10-22 15:30 博理112
Simulation and mitigation approaches for soft errors at advanced technology nodes 演講者:Prof. Bharat BhuvaProfessor|Vanderbilt University
時間:Date:2014-10-22|TIme:15:30
地點:博理112
主辦單位:EDA組
協辦單位:電子所
聯絡人:盧奕璋教授
聯絡電話:
演講內容:
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高整合型驅動IC技術趨勢介紹 謝晉昇經理 2014-10-20 16:30 明達231
高整合型驅動IC技術趨勢介紹 演講者:謝晉昇經理|聯詠科技 移動式產品事業部
時間:Date:2014-10-20|TIme:16:30
地點:明達231
主辦單位:ICS組
協辦單位:電子所
聯絡人:盧信嘉教授
聯絡電話:
演講內容:
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Hardware Security: What IC Designers Can Do Against Existing Threats Noriyuki MiuraProf. 2014-10-13 16:30 明達231
Hardware Security: What IC Designers Can Do Against Existing Threats 演講者:Noriyuki MiuraProf.|神戶大學
時間:Date:2014-10-13|TIme:16:30
地點:明達231
主辦單位:臺大電子所
協辦單位:臺大SOC中心
聯絡人:鄭振牟教授
聯絡電話:
演講內容:
講者介紹:Noriyuki Miura received the Ph.D. degree in electrical engineering from Keio University, Yokohama, Japan in 2007. During  his Ph.D. study and postdoc research activity under Prof. Tadahiro Kuroda’s guidance, he worked for developing inductive-coupling wireless interconnect technology for 3D IC integration. He is currently an assistant professor at Kobe University working o n hardware security, smart sensor, and 3D heterogeneous integration. Dr. Miura has published more than 50 international conference papers including 16 ISSCC papers, and was selected as one of the top ISSCC paper contributors from 2004 to 2013. He is currently serving for Symposium on VLSI Circuits, A-SSCC, ASP-DAC, and VLSI-DAT TPC.
 
演講大綱:Today we manage and store very important and sensitive information in electronic computers i.E. IC chips. Cryptography is one of the powerful tools to protect such sensitive information in a cyber (software) domain. However, the cryptographic processing is anyway finally done in IC hardware. Malicious attackers exploit or break physical weakness of the IC hardware implementations. In this presentation, some existing threats to actual secure hardware electronic devices will be introduced with some countermeasures that we (IC designers) can do against these threats.
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與電子大師對談Meet with Masters on Solid-State Circuit President Bill Bidermann, Prof. Jan Van der Spiegel, Prof. Kenneth C. Smith 2014-10-13 10:00 博理館201會議室
與電子大師對談Meet with Masters on Solid-State Circuit 演講者:President Bill Bidermann, Prof. Jan Van der Spiegel, Prof. Kenneth C. Smith|
時間:Date:2014-10-13|TIme:10:00
地點:博理館201會議室
主辦單位:電子所
協辦單位:電機系
聯絡人:吳佳蓉
聯絡電話:33663700#184
演講內容:
與電子大師對談Meet with Masters on Solid-State Circuit
時間:2014/11/13(四) 10:00-12:30
地點:國立台灣大學博理館201
 
 
特邀貴賓:President. Bill Bidermann, SSCS President
     Prof. Jan Van der Spiegel, SSCS Vice President
     Prof. Kenneth C. Smith, Life Fellow, IEEE
 
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[ICS Seminar]顯示器之驅動IC技術與發展 徐正池副處長 2014-10-06 16:30 明達231
[ICS Seminar]顯示器之驅動IC技術與發展 演講者:徐正池副處長|奇景光電
時間:Date:2014-10-06|TIme:16:30
地點:明達231
主辦單位:ICS組
協辦單位:電子所
聯絡人:盧信嘉敎授
聯絡電話:
演講內容:
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[專題演講] 史記的智慧 呂世浩教授 2014-10-06 13:30 博理113
[專題演講] 史記的智慧 演講者:呂世浩教授|臺大歷史系
時間:Date:2014-10-06|TIme:13:30
地點:博理113
主辦單位:電子所
協辦單位:
聯絡人:魏文儀
聯絡電話:33663530
演講內容:
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(此演講因故取消!!!)QoS Analysis for Network-on-Chip: Methodology, Tightness and Automation Zhonghai LuProf. 2014-07-04 10:00 電機二館142室
(此演講因故取消!!!)QoS Analysis for Network-on-Chip: Methodology, Tightness and Automation 演講者:Zhonghai LuProf.|KTH Royal Institute of Technology, Stockholm, Sweden
時間:Date:2014-07-04|TIme:10:00
地點:電機二館142室
主辦單位:Intel-臺大創新研究中心
協辦單位:台大系統晶片中心/台灣大學電子所
聯絡人:邱玉霜
聯絡電話:0233663718
演講內容:
(此演講因故取消!!!updated 2014.7.1)
 
Abstract:
 
Network-on-Chip (NoC) is becoming an essential architecture as CMPs and SoCs advance from multi-core to many-core era.  Over ten years of NoC research has produced abundant results. However, our understanding on performance guarantees has not advanced as desired, though  NoC cannot be trusted if delay is not proven bounded.  In the past few years, we have taken a formal approach to address the challenge in finding packet delay bound, called QoS analysis. In this talk, we present our QoS analysis methodology, which is based on network calculus and linked to Intel’s xMAS (extensible Micro-Architectural Specification) model.  We address the tightness concern using a heuristic algorithm in a non-conventional way and show that our analysis gives good tightness. Finally, based on the pretty “regular” analysis procedure, we present a prototype tool which turns manual closed-form derivation into automatic calculation of delay bound.
 
Short Bio:
 
Zhonghai Lu is an Associate Professor from KTH Royal Institute of Technology, Stockholm. He was an engineer from 1989 to 2000 working in design of electronic circuits and systems after completing his BSc. from Beijing Normal University. He earned his MSc. and PhD from KTH in 2002 and 2007, respectively.  He also held MBA in Innovation and Growth from University of Turku, Finland, in 2012. He has been working in the Network-on-Chip (NoC) area for over ten years.  Among his NoC projects, he was a Principal Investigator of the research program on “Future of On-Die Communication Fabrics” of Intel Corporation.
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美國能源部Sandia國家實驗室-盧子敏博士將於2014年7月1日至本所演講,歡迎各位師生踴躍參與。 盧子敏博士 2014-07-01 10:20 博理館201會議廳
美國能源部Sandia國家實驗室-盧子敏博士將於2014年7月1日至本所演講,歡迎各位師生踴躍參與。 演講者:盧子敏博士|美國能源部桑迪亞國家實驗室(Sandia National Lab)
時間:Date:2014-07-01|TIme:10:20
地點:博理館201會議廳
主辦單位:電子所
協辦單位:電機系
聯絡人:陳宏銘博士後研究員
聯絡電話:02-33663700#129
演講內容:
演講題目:Silicon-based low-dimensional electronic devices: fabrication, 
          characterization, and their physical behavior in the quantum regime
講者:    盧子敏博士(Dr. Tzu-Ming Lu)
時間:    2014年7月1日(週二)上午10:20-11:20
地點:    博理館201會議廳
聯絡人:  管傑雄教授實驗室-陳宏銘博士後研究員
連絡電話:02-33663700#129
Email:     hungmingchen@ntu.edu.tw
 
講者介紹:
盧子敏博士為1999年奧林匹亞化學競賽金牌得主,畢業於臺大電機系/化學系(雙主修),並於普林斯頓大學獲得電機博士學位。盧博士目前任職於美國能源部桑迪亞國家實驗室(Sandia National Lab),主要研究的領域為量子計算(有關量子計算可參考http://tinyurl.com/mknbbj8http://tinyurl.com/kdrsvh4),本次特地回國與所上師生分享於桑迪亞實驗室的研究現況,歡迎各位師生踴躍參與。
 
關於桑迪亞國家實驗室:
Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.
 
演講大綱:
Low-dimensional electron systems in silicon have been of great importance to both engineers and condensed-matter physicists. Silicon metal-oxide-semiconductor field-effect transistors, for example, are not only one of the fundamental building blocks of modern electronics but also the system in which the quantum Hall effect and the two-dimensional metal-insulator transition were discovered. In this talk, I will discuss my recent experimental work on several silicon-based low-dimensional electron systems, including high-mobility Si/SiGe field-effect transistors, foundry-fabricated Si/SiGe single-electron transistors, and a single donor electron qubit in silicon. The fabrication processes and electrical characterization of these novel devices as well as their intriguing physical behavior in the quantum regime will be presented. The electrical properties of these devices show much promise for a variety of potential applications ranging from high-speed cryogenic electronics to solid-state quantum computing.
(Lu, T-M., N. C. Bishop, L. A. Tracy, R. Blume-Kohout, T. Pluym, J. Wendt, J. Dominguez, J. Means, P. G. Kotula, J. Cederberg, M. P. Lilly, M. S. Carroll)
附加檔案:
Device Performance Investigation of Nanoscale FETs and Other Novel Functional Devices Based on 2D Materials: A Theoretical Perspective Gengchiau Liang 2014-07-01 14:00 博理館101演講廳
Device Performance Investigation of Nanoscale FETs and Other Novel Functional Devices Based on 2D Materials: A Theoretical Perspective 演講者:Gengchiau Liang|National University of Singapore
時間:Date:2014-07-01|TIme:14:00
地點:博理館101演講廳
主辦單位:劉致為教授
協辦單位:電子所
聯絡人:張小姐
聯絡電話:33663700#334
演講內容:
講題:Device Performance Investigation of Nanoscale FETs and Other Novel Functional Devices Based on 2D Materials: A Theoretical Perspective
時間:2014年7月1日星期二,下午2:00~3:00
地點:博理館101演講廳
講者:Gengchiau Liang
   National University of Singapore
   Department of Electrical and Computer Engineering
   Computational Nanoelectronics and Nanodevice Laboratory
 
Abstract
In the last decades, the continuous scaling of silicon planar MOSFETs has successfully enhanced the performance of digital processing systems, such as logic and information devices. Continuing this scaling trend, the channel length of silicon MOSFETs as predicted by ITRS will need to be scaled even further to meet future generation technology requirements. Therefore, numerous advance materials (such as strained silicon, III--‐V channel material, nanowire FETs, graphene--‐based FETs, etc.), and emerging device concepts and technology (tunneling FETs, NEMs, tunneling diode, and spintronic devices, etc.) have been proposed. Among these research devices, two--‐dimensional material, such as graphene related materials, MoS2, etc., have been extensively studied and generated considerable interesting due to their unique electronic and optoelectronic properties. In additions, the interesting spintronic behaviors in several 2D materials, namely spin separation in silicnece and germanene and spin locked in topological materials, also attract a lot of attentions for spintronic device applications.
 
In this talk, therefore, I shall firstly give the introduction to the current development on the FET--‐related devices and novel functional devices. Next, I will discuss the fundamentals of material properties of these advanced 2D materials including graphene and beyond graphene, such as transition metal  ichalcogenides (TMDs), silicene, Bi- 2Se3, etc. Furthermore, I will briefly introduce our general modeling procedure, self--‐consistently solving the Non--‐Equilibrium--‐Green’s--‐Function transport formalism and the device electronic structure. Finally, I apply this model to investigate the device physics/performance of conventional FETs, tunneling FETs, NEMs, spin filters and other potential devices for low power, high performance applications.
 
Biography
Gengchiau Liang received the B.S. and M.S. degrees in physics from the National Tsinghua University, Hsinchu, Taiwan, in 1995 and 1997, respectively, and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, Indiana, in 2005. He was a postdoctoral research associate in electrical engineering at Purdue University, and then, joined the Department of Electrical and Computer Engineering at National University of Singapore, Singapore as an assistant professor. Currently, he is the associate professor, the supervisor of computational nanoelectronics and emerging device group, and the director of computational nanoelectronics and nanodevice laboratory. Furthermore, he also serves as a deputy director of microelectronic technology group in the Department of Electrical and Computer Engineering at National University of Singapore, Singapore.
 
His research emphasizes an interdisciplinary perspective bringing together the discourse of diverse fields of fundamental science and device engineering with the aim of discovering new physical phenomena in nano-materials for enhancing the performance of existing devices and for innovating novel functional devices. He has been involved in the development of a quantitative description of quantum transport for both electrons and phonons through nanoscale systems, and worked on the nano-scale device physics and simulation. The developed theories and models have been employed to understand the physical phenomena of various devices such as interface effects, the details of potential across the molecular junction, graphene based devices, novel functional devices, and carrier transport under magnetic field in general. His current research topics are focused on modeling and theoretical investigation of advanced 2D materials (graphene, and beyond graphene) and their applications, spin caloritronics, topological electronic devices, energy harvesting devices based on thermoelectric properties of nano-devices, low power consumption devices, and nanoscale field-effect transistors.
附加檔案:
【古培正教授光電專題講座:Strain Engineering in GaN Nanostructures】 古培正教授 2014-06-27 10:30 電機二館105室
【古培正教授光電專題講座:Strain Engineering in GaN Nanostructures】 演講者:古培正教授|交通大學光電系
時間:Date:2014-06-27|TIme:10:30
地點:電機二館105室
主辦單位:台大光電創新研究中心
協辦單位: 
聯絡人:侯立萱
聯絡電話:
演講內容:
講題:【古培正教授光電專題講座:Strain Engineering in GaN Nanostructures】
時間:2014年6月27日(星期五),上午10:30
地點:電機二館105室
講者:古培正 (P.C. Ku)
(Current) Department of Photonics, National Chiao Tung University
(Permanent) Department of Electrical Engineering & Computer Science, University of Michigan
 
Abstract:
Strain alters both electronic and optical properties of semiconductors. Properly controlled, strain
can greatly improve device performance. Biaxial strain in III-V semiconductors lowers the
effective mass of their valence band and enables faster transistors and lower-threshold lasers.
Poorly controlled, strain increases defect density and leads to unwanted properties. Strain
induces an anisotropic piezoelectric field in III-nitride semiconductors, which is responsible for
efficiency droop in LEDs, difficulties in achieving green emitters, and abnormally large
linewidth from quantum dot emission. However, properly controlled, strain can also lead to new
frontiers in III-nitride photonics. Specifically, exploiting tight coupling between strain and
piezoelectric field in nitride semiconductor nanostructures can enable an ultracompact RGB
(full-color) light engine for lighting, display, and imaging applications or a chip-scale
polarization-controlled single photon source for quantum cryptography, both of which are
difficult to achieve via other means or materials. In this talk, I will report our recent progress in
this area.
 
Bio:
P.C. Ku is currently a visiting associate professor in the Department of Photonics
at the National Chiao Tung University, Hsinchu, Taiwan. He received all his
degrees in electrical engineering including a BS from the National Taiwan
University and a PhD from the University of California at Berkeley. He was
awarded the Ross Tucker Memorial Award in 2004 as a result of his PhD
research. He had a brief career with Intel from 2004 to 2005 before joining the
University of Michigan in 2006 where he is currently an associate professor of
electrical engineering and computer science. In 2010, he cofounded Arborlight that is dedicated
to solid-state lighting system design and application. He received the DARPA Young Faculty
Award in 2010.
附加檔案:
奈米CMOS電子設計自動化(Nano-CMOS EDA) 張克正副處長 2014-04-28 15:30 博理館112教室
奈米CMOS電子設計自動化(Nano-CMOS EDA) 演講者:張克正副處長|台灣積體電路製造股份有限公司 設計暨技術平台 (DTP)
時間:Date:2014-04-28|TIme:15:30
地點:博理館112教室
主辦單位:電子工程學研究所
協辦單位:台積電-臺灣大學聯合研發中心
聯絡人:蔡坤諭教授
聯絡電話:
演講內容:
摘要:
人類在21世紀的第一年,即2000年,正式進入130奈米CMOS與銅製程的大量生產哩程碑。現在是2014年,人類已有28奈米、20奈米、與16/14奈米製程。這些奈米CMOS將是2014年至2018年的電子產品的主流。
 
奈米CMOS研發可以比喻是要在近年內在一百公里以上的彎曲道路上,用約五十奈米寬的銅線(人類頭髮寬度的千分之一)把一百億個電晶體全部接好。而且在五年內這些銅線與電晶體都不能斷裂,持續傳輸穩定的電壓與電流。這是發揮創新,使電磁學軟體與統計學軟體同時幫助奈米半導體晶片設計提高良率,這也是本演講的主要內容。
 
奈米CMOS應該算是近幾年最有活力、發展最快速之跨領域科學與工程。各種不同背景,包含材料、生物科技、醫學、化工、物理、化學、電子、電機、資訊、機械等領域之科學家與工程師,正在進行奈米CMOS相關晶片設計。智慧型手機與平板電腦就是最明顯的例子。重賞之下必有勇夫,相信在近年內,台灣能夠培養出更多奈米CMOS電子設計自動化的人材,來幫助奈米CMOS產業的研究與發展。
 
講員簡傳:
張克正博士目前在新竹台積電總部設計暨技術平台部門(DTP)研發電子設計自動化(EDA)軟體。他曾在國立清華大學資訊工程學系任職九年半,教授與CMOS相關的EDA與電路設計課程,並且研究EDA軟體、發展奈米CMOS電路可生產性設計(DFM)技術、與執
行高頻電子電路設計。他在清大服務期間,曾指導30多位研究生共同發表數十篇IEEE論文,並獲得六件美國與亞洲電子設計自動化相關專利。
 
張博士在1983年獲得國立台灣大學電機系學士與碩士學位後,到美國加州大學洛杉磯分校(UCLA)研究電子電路設計自動化軟體。他在1989年拿到電腦科學博士學位後,曾在美國加州矽谷的惠普電腦公司總部(Hewlett-Packard Company)從事高頻CMOS電路設計自動化軟體與高頻電子電路DFM研發。他後來與多位矽谷的朋友共同進行CMOS相關高科技創業與行銷,並於2003年回國,陸續在國立清華大學與台積電總部任職至今。
 
35個學生最常提問的問題:
1.     在台積電的IC設計部門工作和在IC Design House有甚麼不同?
2.     有純粹IC Design嗎? 還是需要跟製程配合?
3.     先進製程的研發是看客戶需求?還是自我挑戰?
4.     非電子電機科系,如通訊/光電等畢業的同學在DTP有工作機會嗎?
5.     工作之餘,可以用台積的設計法則做自己想做的電路嗎
6.     申請DTP需要那些專業知識或特質
7.     學長工作一年遇到最大的困難是甚麼? 當時怎麼解決
8.     在RD和Operations單位,薪資福利是否有差異?
9.     RD單位的工時?工程師的主要壓力來源是甚麼?
10.   RD工程師工作內容?平均工時?需輪班?進無塵室的頻率?
11.   聽說tsmc要自己做設備,設備的工作內容有研發嗎? 博班做設備適合嗎?
12.   2008景氣不好的時候,工程師薪水是否受影響? 研發單位是否比較閒?
13.   有機會外派海外嗎?
14.   碩/博士的差異
15.   碩士/博士的工作定位有什麼差別? 是否同工不同酬?
16.   碩士/博士進公司後職等不同,是否會影響升遷?
17.   台積電對博士人才的需求如何?  Fab端會錄用博班學生嗎?
18.   土博士和洋博士在公司的發展和晉升有差異嗎
19.   對於外界說台積電工程師很操的說法,你們的看法是?
20.   對於一周工作50小時,台積電有沒有實際的做法?
21.   台積電選才比較重視專業還是人格特質要具備何種特質或優勢才能拿到RDSS的聘書呢?
22.   對於工作地點的偏好會被列入考量嗎? 我想留在台中工作, 就真的可以面試台中的機會嗎?
23.   請問面試會問什麼問題?
24.   可不可以先不管部門,進台積電後再想辦法內部轉職進自己想去的部門?
25.   研發替代役的工作輪調機會是否等同正式員工?
26.   學長進入產業界後,對於學界的paper看法是甚麼? 會覺得學界做的和產業有很大的差距嗎?
27.   是否有buddy不想帶領徒弟,讓新人被孤立
28.   RD及DTP會在南科設立部門嗎
29.   員工福利有哪些?
30.   在全球化競爭下的TSMC Strategy
31.   對台積電在2015年之後的趨勢看法如何
32.   目前經濟衰退對台積未來營運的影響是?
33.   摩爾定律是否已走到終點?台積電RD的Career Path? 半導體研發未來的挑戰是?
34.   台積電目前世界排名第三,明年是否有機會超越三星或Intel?
35.   三星在DRAM的技術上,是否已超越台積電?
 
附加檔案: Download
TSMC校園講座: 智慧 生活的原動力 – 半導體電子 孫元成研發副總經理暨技術長 2014-03-06 10:30 博理101
TSMC校園講座: 智慧 生活的原動力 – 半導體電子 演講者:孫元成研發副總經理暨技術長|台積電
時間:Date:2014-03-06|TIme:10:30
地點:博理101
主辦單位:台積電中心
協辦單位:電子所、台灣半導體協會(TSIA)、智慧電子國家型科技計畫辦公室(NPIE)
聯絡人:黃小姐
聯絡電話:3366-1783
演講內容:
智慧生活的原動力 – 半導體電子 (暫定 )

 
為強化 產學 之間的 合作 、培養 、培養未來國際級半導體領袖人才 未來國際級半導體領袖人才 ,台灣半導體協會(TSIA) 、智慧電子國家型科技計畫辦公室 (NPIE)、台灣大學電子所(GIEE)以及台積電 —臺灣大學聯合研發中心(TSMC -NTU Center)在 2014 年將推出一系列的校園演講活動。第一場活動特別邀請到台積電研發副總經理暨技術長 -- 孫元成博士擔任講者。
 
 
本場演講中,孫副總將帶領聽眾一窺智慧生活的原動力 、讓您了解半導體電子對於實踐智慧生活所扮演的關鍵 角色。此外,針對 未來有志於半導體 產業的學子,孫副總也將揭露半導體 科技人才的職涯發展 可能性, 以及有關薪酬、福利 、友善就業環境 等資訊,並提醒學子們未來半導體產業所需的人才條件。
 
藉由本次演講,同學們可望快速了解半導體電子如何開創智慧生活的現況與未來、產業所需解決方案,同時也有機會了解台積電中心為此提供的一系列學生方案 ,有助於您盡早將所學 /研究結合產業技術需求進行規劃 , 歡迎同學 (特別是 電機、物理材料化學工資及數等科系 )報名參加。

主辦單位: 台灣半導體協會、智慧電子國家型科技計畫辦公室、 臺灣大學電 子所、台積-- 臺灣大學聯合研發中心 臺灣大學聯合研發中心
時間:2014年3月6日上午10:30-12:30 (備餐)
地點:博理館101 室
對象:學生
報名 方式 :請至 myNTU活動報名系統(https://info2.ntu.edu.tw/register/flex/main.html?actID=2014J800_01)
聯絡人 :黃小姐 Tel: 3366 -1783 ; E -mail: allisonhhuang@ntu.edu.tw
 
附加檔案:
Beyond Silicon CMOS Technology Based on High-Mobility Channel 馬佐平院士 2014-02-12 14:00 BL201
Beyond Silicon CMOS Technology Based on High-Mobility Channel 演講者:馬佐平院士|(耶魯大學工程與應用科學院
時間:Date:2014-02-12|TIme:14:00
地點:BL201
主辦單位:電資學院
協辦單位:電子所、電機系
聯絡人:吳小姐
聯絡電話:
演講內容:
主講人簡介:
Professor Ma is Raymond John Wean Professor of Electrical Engineering at Yale University. Prof. Ma also serves as a Co-Director of the Yale Center for Microelectronics, and a Co-Director of the Yale-Peking Joint Center for Microelectronics and Nanotechnology. He is also a Professor of Applied Physics. Prof. Ma was the Chairman of the Electrical Engineering Department from July,1991, to June, 1996, and from July 2000 to June 2007. Prof. Ma was elected a member of the National Academy of Engineering (NAE) in 2003.
 
Prof. Ma has been actively involved in organizing, chairing, or serving as a committee member of numerous technical conferences, including the IEEE/SISC, IEEE/DRC, IEEE/NSREC, VLSI-TSA, SSDM, EDMS, ICSICT, ECS, and MRS meetings. He was the Symposium Chair of the 1999 International VLSI-TSA Symposium held in Taipei June 1999 and, since 2001, is a member of this Symposium's Steering Committee.

T.P. Ma has served as a consultant for industry worldwide. He has also been the Principal Investigator of joint R & D projects with numerous high-tech companies worldwide, including IBM, Intel, Motorola, TI, Sematech, Micron Technologies, Lucent Technology, GE, AMD, Hughes, LSI Logic, Rockwell Semiconductors, JPC, ATMI, PSS, Philips, Siemens, Hitachi, NEC, Toshiba, Mitsubishi Electric, Macronix, and TSMC.
附加檔案:
Sequential Equivalence Checking for Clock-Gated Circuits Alan Mishchenko研究員 2014-01-27 14:00 電二144
Sequential Equivalence Checking for Clock-Gated Circuits 演講者:Alan Mishchenko研究員|UC Berkeley
時間:Date:2014-01-27|TIme:14:00
地點:電二144
主辦單位:台大電子所
協辦單位:台大電機系
聯絡人:江介宏
聯絡電話:33663685
演講內容:
Abstract:
Often sequential logic synthesis can lead to substantially easier verification problems, compared to the general-case for sequential equivalence checking (SEC). This talk discusses conditions when SEC can be reduced to combinational equivalence checking (CEC). These can be applied to many sequential clock gating transforms, where correctness is argued intuitively using a finite unrolling of a sequential design. A method based on these theorems was applied to six large industrial examples. It completed on all examples and was about 30x faster on the three examples where the conventional engine was able to finish.

Reference:
This talk is based on FMCAD'10 paper 
http://www.eecs.berkeley.edu/~alanmi/publications/2010/fmcad10_sec.pdf
with a few new insights from the TCAD'14 paper:
http://www.eecs.berkeley.edu/~alanmi/publications/2014/tcad14_cg.pdf

Bio:
Alan Mishchenko graduated from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. From 1998 to 2002 he was an Intel-sponsored researcher at Portland State University. In 2002, he joined the EECS Department at UC Berkeley, where he is currently an associate researcher at Berkeley Verification and Synthesis Research Center (BVSRC). Alan is interested in developing efficient algorithms for logic synthesis and formal verification. 
附加檔案:
「終極王牌特訓班-高速串列測試之最後進擊」─接收器完整性信號分析的測試原理與應用 Eric Shen 2014-01-22 14:00 電機二館124會議室
「終極王牌特訓班-高速串列測試之最後進擊」─接收器完整性信號分析的測試原理與應用 演講者:Eric Shen|
時間:Date:2014-01-22|TIme:14:00
地點:電機二館124會議室
主辦單位:太克科技
協辦單位:台大電子所
聯絡人:李小姐
聯絡電話:
演講內容:
預加重(Pre-emphasis)及 均衡器(Equalizer)的使用,在接收器及傳送器的測試上,隨著信號速度的增加,FR4板材的使用極限,而越顯得重要, 如何了解接收器的測試原理,並進而針對接收端線路進行除錯,損耗補償及改善, 在接收器的信號完整性分析上佔有極大部份的效用
附加檔案:
The Evolution of CMOS Device Architecture for Microelectronic Applications 林崇勳博士 2013-11-27 11:00 電機二館101室
The Evolution of CMOS Device Architecture for Microelectronic Applications 演講者:林崇勳博士|
時間:Date:2013-11-27|TIme:11:00
地點:電機二館101室
主辦單位:電子所劉致為教授
協辦單位:電機系
聯絡人:李小姐
聯絡電話:33663700#334
演講內容:
It is getting harder to fully turn the transistors off in the conventional CMOS scaling approaches due to the short channel effects. FinFET has been considered as the promising candidate to extend CMOS scaling beyond the sub-22nm node because of superior electrostatic control and lower sensitivity to random dopant fluctuations. This enables a robust low-Vdd design spectrum using FinFET technology. Other exploratory device architectures such as Si nanowire, ETSOI, Ge/III-V channel device, and carbon-based device, are under investigated to take over FinFETs for the future nodes. In this talk, we will address the device design consideration of different device architectures for 14nm node and beyond.
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MIMO Communications: From Bounds to VLSI Implementation Heinrich Meyr榮譽退休教授 2013-10-23 10:30 台大電機二館229室
MIMO Communications: From Bounds to VLSI Implementation 演講者:Heinrich Meyr榮譽退休教授|RWTH Aachen
時間:Date:2013-10-23|TIme:10:30
地點:台大電機二館229室
主辦單位:INTEL-台大創新研究中心
協辦單位:台灣大學電子所/台大系統晶片中心
聯絡人:邱小姐
聯絡電話:33663718
演講內容:
Abstract
     The exponential growth of data rates for mobile applications is driven by progress in both domains of communication algorithms and technology. A communication technology promising a continuation of exponential data rate growth is MIMO which uses multiple antennas at both receiver and transmitter to transmit multiple data streams at the same time over the same frequency band.  Two different approaches exist in MIMO. The first approach employs “massive signal processing”to implement the ultra-complex receiver algorithms with ultra-energy efficient VLSI circuits. The other approach, “massive MIMO”, proposes antenna arrays with many hundred antennas at the base stations that enable nearly optimal simple linear processing algorithms.
     We begin our talk with a brief overview of the massive MIMO approach. In the main part of this lecture we discuss the massive signal approach and introduce the optimal ML receiver algorithm.  We discuss the design, and its corresponding design methodology, of the world-wide first VLSI implementations of an optimal iterative MIMO receiver. Working silicon has been fabricated in 65nm technology and has been fully tested in 2012 by the collaboration between researchers of ETH Zürich, EPFL and RWTH Aachen.
     The message of the talk will be that the design of advanced communication systems mandatorily requires to jointly consider the multidimensional design space comprising algorithm and architecture. We will discuss the trade-offs between communication performance and architectural efficiency metrics, such as area, energy efficiency and flexibility/programmability. While the results are specific, the lessons learned have shown to be useful for helping to bridge the gap between signal processing theory and VLSI implementation in other applications. 
 
Biography
     Dr. Meyrreceived his M.Sc. and Ph.D. from ETH Zurich, Switzerland. He spent over 12 years in various research and management positions in industry before accepting a professorship in Electrical Engineering at Aachen University of Technology (RWTH Aachen) where he founded the Institute for Integrated Signal Processing Systems. In 2007 he has assumed the rank of emeritus but remains active as a researcher.  Dr. Meyrhas been a visiting Professor at UC Berkeley, ETH Zürich and EPFL. In 2013 he has been appointed as a “Grand Professor” at cfaed(centre for advancing electronic design) at TU Dresden.
      During the last 40 years, Dr. Meyrhas worked extensively in the areas of communication theory, digital signal processing and CAD tools for system-level design.  Dr. Meyrhas received several IEEE best paper awards.  He is the recipient of the prestigious “Vodafone Innovation Prize” for the year 2000. He is a Life-Fellow IEEE.
     Dr.Meyrhas a dual career as an entrepreneur. He has founded several successful companies. The last company he has cofounded in 2001 was LisaTekwhich merged with CoWarein 2003.  In 2010  CoWarewas acquired by Synopsys. . Dr. Meyrhas also been a board member of large international companies located in Switzerland and the US.
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Robust Computing 胡玉衡教授 2013-10-18 14:00 電機二館142會議室
Robust Computing 演講者:胡玉衡教授|University of Wisconsin – Madison/ Dept. Electrical and Computer Engineering
時間:Date:2013-10-18|TIme:14:00
地點:電機二館142會議室
主辦單位:Intel-台大創新研究中心
協辦單位:台大電子所
聯絡人:邱小姐
聯絡電話:33663718
演講內容:
講者介紹:
 Yu Hen Hu received BSEE from National Taiwan University, Taiwan ROC in 1976, and MSEE and PhD degrees from University of Southern California, Los Angeles, CA, USA in 1982.  He was in the faculty of the Electrical Engineering Department of Southern Methodist University, Dallas, Texas. Since 1987, he has been with the Department of Electrical and Computer Engineering, University of Wisconsin, Madison where he is currently a professor.
    Dr.  Hu's has broad research interests ranging from design and implementation of signal processing algorithms, computer aided design and physical design of VLSI, pattern classification and machine learning algorithms, and image and signal processing in general. He has published more than 300 technical papers, edited or co-authored four books and many book chapters in these areas.
    Dr. Hu has served as an associate editor for the IEEE Transaction of Acoustic, Speech, and Signal Processing, IEEE signal processing letters, European Journal of Applied signal Processing, Journal of VLSI Signal Processing, and IEEE Multimedia magazine. He has served as the secretary and an executive committee member of the IEEE signal processing society, a board of governor of IEEE neural network council representing the signal processing society, the chair of signal processing society neural network for signal processing technical committee, and the chair of IEEE signal processing society multimedia signal processing technical committee.  He was also a steering committee member of the international conference of Multimedia and Expo on behalf of IEEE Signal processing society.
    Dr. Hu is a fellow of IEEE.  
 
演講大綱:
With continued shrinkage of transistor sizes, it is more and more difficult to maintain error free computing in next generation micro-processor architectures. To ensure reliable computing outcome, on the one hand, error correcting measures such as coding, redundancy will be incorporated. On the other hand, for application specific tasks, the tolerable performance range should also be exploited to achieve desired performance at least implementation and operating cost in terms of both delays and power consumption. This observation has led to numerous works touting approximate computing, stochastic computing, soft computing, etc.
      In this presentation, these recent progresses will be surveyed, and their relations to traditional fault-tolerant, dependable computing will also be investigated. We plan to show that this new development can be framed in the well-known design space exploration paradigm in that the robustness of computing outcomes will now be an additional performance metric to be optimized jointly with the power and delay. Examples of robust computing in terms of algorithm transformation, numerical analysis, and relations to statistical estimation will be provided as well. 
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A 10-Bit 1-GHz ADC Using Charge-Steering Op Amps Professor Behzad Razavi 2013-09-12 17:00 博理館101會議廳
A 10-Bit 1-GHz ADC Using Charge-Steering Op Amps 演講者:Professor Behzad Razavi|University of California, Los Angeles
時間:Date:2013-09-12|TIme:17:00
地點:博理館101會議廳
主辦單位:國立台灣大學-聯發科技無線研究實驗室/IEEE SSCS Taipei Chapter/國立台灣大學電子工程學研究所
協辦單位:國立台灣大學電機工程學系 /國立台灣大學系統晶片中心
聯絡人:李小姐
聯絡電話:33663700#367
演講內容:
The raw performance of pipelined ADCs primarily hinges upon that of their
constituent op amps. The voltage gain and output swing limitations imposed by
technology and supply scaling have motivated various digital correction
techniques that afford the use of low-gain op amps in high-resolution ADCs
Recent designs have progressively reduced the residue amplifier complexity and
gain, eventually reaching a simple resistively-loaded differential pair with
capacitive feedback.

This work explores the notion of charge steering in the design of op amps and
ADCs. It is shown that charge-steering op amps offer significant advantages over
their continuous-time counterparts. A pipelined ADC employs charge-steering op
amps to relax the trade-offs among speed, noise, and power consumption. Applying
full-rate nonlinearity and gain error calibration, a prototype realized in 65-nm
CMOS technology exhibits a Nyquist SNDR of 52.2 dB and draws 22.8 mW at 1 GHz.
The ADC also demonstrates a new histogram-based background calibration
technique.
附加檔案: Download
Analog Design Challenges on Logic Processes Gregory F. Taylor Director/ Intel Fellow/ 2013-06-06 14:20 電機二館105室
Analog Design Challenges on Logic Processes 演講者:Gregory F. Taylor Director/ Intel Fellow/ |Intel
時間:Date:2013-06-06|TIme:14:20
地點:電機二館105室
主辦單位:台大電子所
協辦單位:Intel台大創新研究中心,台大系統晶片中心
聯絡人:邱玉霜
聯絡電話:33663718
演講內容:
演講大綱:
    This presentation examines issues in the use of analog circuits on logic process technologies. It goes over trends in demand for analog capabilities on microprocessors, logic process technology scaling impact on analog transistor performance, and some of the challenges faced by analog circuits beyond those necessary for digital operation. Current approaches to these challenges are outlined, along with some of the limitations of those approaches.
 
講者簡介:
    Greg Taylor is an Intel Fellow and director of the System-on-a-Chip (SoC) Design Lab in the Integrated  Platforms Research Lab in Intel Labs. His interests include Systems on a Chip, Analog/Mixed Signal circuits, and Wireless.

Taylor joined Intel in 1991 and has held several senior design engineering positions working on 10 generations of microprocessors including members of Intel's Pentium®, Pentium® II, Pentium® III, and Intel NetBurst® microarchitecture families. Prior to joining Intel, he worked as a principal engineer at Bipolar Integrated Technology.

Taylor has received an Intel Achievement Award for his work on deploying advanced packaging. He has published over 60 papers and holds over  60 patents on integrated circuit design and test. Taylor is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Taylor received his doctorate in computer and systems engineering in 1985 from Rensselaer Polytechnic Institute. His graduate work was  completed with the support of a Fellowship from the Fannie and John Hertz Foundation.

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Precise Analysis of Programs with Numeric Data Types Anthony W. Lin Dr. 2013-05-30 13:30 225 Ming-Dar Hall
Precise Analysis of Programs with Numeric Data Types 演講者:Anthony W. Lin Dr.|University of Oxford
時間:Date:2013-05-30|TIme:13:30
地點:225 Ming-Dar Hall
主辦單位:NTU GIEE
協辦單位:NTU EE Dept.
聯絡人:Jie-Hong R. Jiang
聯絡電話:
演講內容:
ABSTRACT:
Automatic analysis of integer-manipulating programs is a main problem in program analysis. Such programs are a basic building block of more complex imperative programs (e.g. with linked lists or strings) since analysis of the latter can often be reduced to analysis of the former (e.g. by some variants of counter abstractions). Since they are already Turing-complete, the challenge is to devise approximation techniques that give useful answers in many cases. In this talk, I will present an automata-based approach to statically analyse programs with numeric data types (based on Minsky\'s counter machines as the basic model). I will then introduce an approximation technique for analysing Minsky\'s machines (called "reversal-bounded analysis") that turns out to be sufficiently powerful for identifying erroneous runs for a large class of programs. Our technique reduces the analysis to an SMT problem, which can then be solved using highly-optimized SMT solvers like Microsoft Z3. We have implemented a prototype and shows the efficacies of the technique on a few interesting examples (e.g. buffer overflow vulnerabilities derived from Linux device drivers). This is a joint work with Matthew Hague, which has appeared in CAV'11 and CAV'12.

BIOGRAPHY:
Anthony W. Lin received his PhD from University of Edinburgh\'s School of Informatics in 2010 under the supervision of Leonid Libkin and the co-supervision of Richard Mayr. His PhD thesis concerns generic and specific techniques for infinite-state model checking. He is currently an EPSRC Postdoctoral Research Fellow at Oxford University Department of Computer Science. His main interests lie in developing theoretically sound and practically applicable techniques in formal verification (especially with applications in program analysis and more recently on language-based security), utilizing techniques from logic and automata. He was awarded LICS 2010 Kleene Best Student Paper Award for his paper titled "Parikh Images of Grammars: Complexity and Applications".
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Science and Technology of Wide Band-gap semiconductor SiC Dr. Hiroyuki Matsunami榮譽教授 2013-05-17 15:00 BL216
Science and Technology of Wide Band-gap semiconductor SiC 演講者:Dr. Hiroyuki Matsunami榮譽教授|京都大學
時間:Date:2013-05-17|TIme:15:00
地點:BL216
主辦單位:劉致為教授
協辦單位:電子所
聯絡人:李小姐
聯絡電話:33663700#334
演講內容:
5月17日(五)將邀請到京都大學榮譽教授─ Hiroyuki Matsunami博士來台大演講,Hiroyuki Matsunami博士將分享包含Epitaxial Growth、Ion Implantation、Schottky Barrier Diodes及Issues in SiC MOSFET Interface等相關技術之最新進展,此次機會非常難得,期望各位同學能夠共襄盛舉。
 
(座位有限,自由入場限額28名,請即早入場,謝謝!)
 
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Silicon nanophotonics-some circuit design considerations Dr. Ron Ho 2013-05-02 15:30 電機二館142會議室
Silicon nanophotonics-some circuit design considerations 演講者:Dr. Ron Ho|
時間:Date:2013-05-02|TIme:15:30
地點:電機二館142會議室
主辦單位:國立台灣大學-聯發科技無線研究實驗室/IEEE SSCS Taipei Chapter/國立台灣大學電子工程學研究所
協辦單位:國立台灣大學電機工程學系 /國立台灣大學系統晶片中心
聯絡人:李小姐
聯絡電話:33663700#367
演講內容:
Silicon nanophotonic links have recently captured the attention of designers interested in their potential energy, area and performance advantages over electrical links. An abstracted view of a silicon nanophotonic link is straightforward, and lends itself nicely to simple and useful system models. Unsurprisingly, however, the realities of building operating photonic links contains several subtleties that are worth understanding. In this talk we will introduce photonic links, discuss their basic operation, and describe the principal physical challenges in their use. These will include resonant ring modulator tradeoffs, ring thermal stability control, efficient receiver designs, and receiver BER vs SNR.
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Challenges and Emerging Solutions in Testing 2.5D- and 3D-Stacked ICs Erik Jan MarinissenPrincipal Scientist 2013-04-25 10:30 博理館201室
Challenges and Emerging Solutions in Testing 2.5D- and 3D-Stacked ICs 演講者:Erik Jan MarinissenPrincipal Scientist|IMEC
時間:Date:2013-04-25|TIme:10:30
地點:博理館201室
主辦單位:電子工程學研究所
協辦單位:台大系統晶片中心
聯絡人:邱玉霜
聯絡電話:33663718
演講內容:
Seminar at NTU
Thursday April 25, 10:30-12:00
@ BL 201
 
Challenges and Emerging Solutions in Testing 2.5D- and 3D-Stacked ICs
 
 
Erik Jan Marinissen
Principal Scientist - IMEC
 
Abstract
Fine-pitch micro-bumps and Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects, thereby enabling the creation of 2.5D- and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D- and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this talk, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access, and will address all of them.
 
Biography
Erik Jan Marinissen is Principal Scientist at IMEC vzw in Leuven, Belgium. Previously, he worked at NXP Semiconductors and Philips Research, both in Eindhoven, the  Netherlands. Marinissen holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992), both from Eindhoven University of Technology. Marinissen’s research interests include all topics in the domain of test and debug of micro-electronics. He is co-author of over 180 journal and conference papers and co-inventor on ten granted US and EP patent families. Marinissen is recipient of the ITC 2008 and ITC 2010 Most Significant Paper Awards and Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop 2002. He served as Editor-in-Chief of IEEE Std 1500 and as Founder and Chair of IEEE P1838 on 3D test access. He is a founder of workshops on ‘Diagnostic Services in Network-on-Chips’ (DSNOC), ‘3D Integration’, and ‘Testing of Three-Dimensional Stacked Integrated Circuits’ (3D-TEST). He serves on numerous conference committees, including ATS, DATE, ETS, ITC, and VTS, and on the editorial boards of IEEE Design & Test of Computers, IET Computers and Digital Techniques, and Springer’s Journal of Electronic Testing: Theory and Applications (JETTA). Marinissen is a Fellow of IEEE and Golden Core Member of Computer Society.
附加檔案: Download
The Fourth Age of Wireless and the Coming of Internet of Everything Thomas H. LeeProfessor 2013-04-23 14:00 博理館101演講廳
The Fourth Age of Wireless and the Coming of Internet of Everything 演講者:Thomas H. LeeProfessor|Stanford University
時間:Date:2013-04-23|TIme:14:00
地點:博理館101演講廳
主辦單位:國立台灣大學-聯發科技無線研究實驗室/IEEE SSCS Taipei Chapter
協辦單位:國立台灣大學電機工程學系 / 國立台灣大學電子工程學研究所/國立台灣大學系統晶片中心
聯絡人:李小姐
聯絡電話:33663700#367
演講內容:
 

 The Fourth Age of Wireless and the Coming of Internet of Everything

The evolution of wireless has followed a clear pattern that tempts us to extrapolate. 

Marconi‘s station-to-station spark telegraphy gave way to a second age dominated by station-to-people broadcasting, and then to today’s ubiquitous people-to-people cellular communications. Each new age became more important and more valuable than the previous age by enlarging the circle of conversants. Because the three ages have covered all combinations of “stations” and “people,” one might be tempted to argue that we have essentially reached the end of history. However, history never ends, so we must assume that there will be a fourth age. But how can that be? One likely answer is that this Fourth Age will involve another enlarging of the circle of conversants by interconnecting inanimate objects. This talk will describe how the inclusion of multiple billions of objects, coupled with a seemingly insatiable demand for ever-higher data rates, will stress an infrastructure built for the Third Age. Overcoming the challenges of the coming Fourth Age of Wireless to create the Internet of Everything represents a huge opportunity for RF engineers. History is not done.

 
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Challenges and Solutions for Embedded SRAM Design 張琮永Jonathan Chang博士 2013-04-18 14:20 電機二館104室
Challenges and Solutions for Embedded SRAM Design 演講者:張琮永Jonathan Chang博士|台灣積體電路製造股份有限公司
時間:Date:2013-04-18|TIme:14:20
地點:電機二館104室
主辦單位:台大電子所
協辦單位:
聯絡人:邱玉霜
聯絡電話:
演講內容:
Abstract:
Embedded SRAM continues to be critical technology enabler for wide range of applications from computing servers to mobile devices.  SRAM is also a key indicator for technology leadership of advance process nodes.  The key challenges for SRAM include Vccmin, leakage and dynamic power reduction, bit cell performance and relentless drive of Moore’s law to achieve 50% scaling for every generation.  As technology scaling approaches sub 10nm, device variation has made it difficult to scale the bit cell size and Vccmin.  New transistors such as finfet have become critical in enabling bit cell scaling and low voltage operation.  Design solutions such as read/write assist have been adopted since 32nm technology to improve Vccmin performance.  Designers started using bit cells beyond conventional 6T SRAM bit cell to achieve low Vccmin.  Dual rail SRAM design emerges as an effective solution to enable DVFS (dynamic voltage frequency scaling) by decoupling logic supply rails from SRAM and thus allowing much wider operating window.  As technology continues to scale, leakage and dynamic power reduction is critical to keep products within the same power envelop as approximately 2x amount of bit cells are placed at the same area between generations.  Sleep transistors and fine grain clock gating have been used for leakage and dynamic power reduction.  This seminar will cover the fundamental of SRAM design to the latest challenges and solutions to enable the continuous scaling of SRAM in advance technology.
 
Bio:
Jonathan Chang is a director leading SRAM IP development at TSMC. He is responsible for delivering SRAM compilers, custom SRAM IPs for low power, high speed applications for advance technology nodes. Jonathanjoined Intel Corporation, Santa Clara, CA in 1998 and since has been engaged in the design of several high-performance microprocessors with emphasis in large, high-speed, low power cache design.  He was a Principal Engineer in the area of cache design in Enterprise Microprocessor Group. In 2010, Jonathan joined TSMC, Hsin-Chu, Taiwan. 
 
Jonathanis a senior member of the IEEEand serves as a technical program committee member of Memory subcommittee for ISSCC since 2013. Jonathan also was the NAE (North America and Europe) technical program committee member of 2011 VLSI symposium on circuits and associate editor of IEEE Trans on VLSI.  Jonathan has published 20+ technical papers in IEEE conferences or journals. 
 
Jonathan Chang received the B.S. degree in electrical engineering from National Taiwan University, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA.
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Opportunities and Challenges of 3-D IC System Architecture and Design 李憲信博士/教授 2013-04-11 14:20 電機二館104室
Opportunities and Challenges of 3-D IC System Architecture and Design 演講者:李憲信博士/教授|台灣積體電路製造股份有限公司/美國喬治亞理工大學
時間:Date:2013-04-11|TIme:14:20
地點:電機二館104室
主辦單位:台大電子所
協辦單位:
聯絡人:邱玉霜
聯絡電話:
演講內容:
Abstract
As device scaling faces several fundamental changes due to physical limitations, interposer-based 2.5D design as well as die-stacked 3D integration are emerged as the frontrunner technologies to continue Gordon Moore’s prophecy in the vertical dimension. It enables a true System-on-Chip design style by stacking multiple die, fabricated with either homogeneous or heterogeneous processes, onto the same package using micro-wires and/or 3-D inter-die vias or through-silicon vias (TSV). This highly anticipated solution not only packs more transistors for a given footprint, it could also offer several potential advantages, e.g., high memory bandwidth, low power consumption, fast interconnect, flexibility in integration, and a much smaller form factor of a system, etc. Nevertheless, to exploit the maximum potential of this novel integration and packaging technology, the logistics of the system design must be reconsidered and re-evaluated to leverage the effective use of 3D vias. In this talk, I will discuss the design opportunities, caveats, and challenges of 3-D stacked IC technology from the perspective of a computing architecture and system design. I will also discuss the experiences and lessons we learned from our prior 3D-MAPS many-core chip fabricated by GlobalFoundries and Tezzaron. Also will be covered is the latest Chip-on-Wafer-on-Substrate (CoWoS) technology offered by TSMC and the design approaches with JEDEC’s wide I/O DRAM.
 
Speaker Bio
 
Dr. Hsien-Hsin Sean Lee is a department manager at the Design and Technology Platform at TSMC. He is currently on leave from Georgia Tech where he was an associate professor at the School of Electrical and Computer Engineering since 2002. His research interests include computer architecture, low-power microelectronics, and 3-D IC. Prior to academia, he was a senior CPU architect at Intel working on Pentium Pro and Pentium III processor (1995-99) and a research staff member working on Itanium processor (1999-2001). He later became an architecture manager of the StarCore DSP center, a joint venture by Lucent/Agere and Motorola leading their SC-140E development and its proliferation for 3G infrastructure (2001-02). Dr. Lee’s Ph.D. research received the Horace H. Rackham Distinguished Dissertation Award from the University of Michigan. At Georgia Tech, he received the DOE Early CAREER PI Award, the NSF CAREER Award, the Georgia Tech ECE Outstanding Jr. Faculty Award, and an IBM Faculty Award. He has published 2 book chapters and more than 90 technical articles including four papers that won the Best Paper Award (MICRO-33, CASES-04, IBM PAC2’05, ANCS-11), four nominated for the Best paper Award (MIT HPEC-07, FPL-07, ICCAD-09, IEEE TCAD 2010) and one selected in IEEE MICRO Top Picks. He holds four U.S. patents and is a senior member of both the IEEE and the ACM.
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Monolithic Wideband and mm-Wave Transceivers and Antenna Arrays Hossein HashemiProfessor 2012-12-24 09:30 電機二館105教室
Monolithic Wideband and mm-Wave Transceivers and Antenna Arrays 演講者:Hossein HashemiProfessor|
時間:Date:2012-12-24|TIme:09:30
地點:電機二館105教室
主辦單位:IEEE SSCS Taipei Chapter、臺灣大學-聯發科技無線研究實驗室
協辦單位:交通大學電子工程學研究所、台灣大學電子工程學研究所
聯絡人:李小姐
聯絡電話:33663700#367
演講內容:
課程內容:
Advancements in semiconductor technology has led to monolithic realization of complex Radio Frequency (RF) Integrated Circuits (IC) and System-On-a-Chip (SOC) for commercial wireless communications. Shannon’s capacity theorem states that the communication data-rate is proportional to the information bandwidth and the logarithm of Signal-to-Noise-plus-Interference Ratio (SNIR). Wireless transceivers operating at higher carrier frequencies have access to larger bandwidth and enable more compact realization (due to smaller wavelength). Antenna arrays can improve the SNIR by dynamically focusing the transmit power towards the desired directions (beam forming), reducing the interferences through spatial filtering, and improving the receiver sensitivity. Antenna arrays have been around for over half a century in high performance military radar and communication systems in the context of phased arrays. Recent research, less than a decade old, has demonstrated monolithic realization of antenna array transceivers in silicon processes, and compact packaged solutions with antenna arrays, for commercial applications such as reliable ultra-high-speed wireless communications at 24 and 60 GHz Industrial Scientific Medical (ISM) bands, low-cost automotive radars at 24 GHz and 77 GHz bands, Ultra-Wide Band (UWB) imaging systems in the 3 – 10 GHz band, and passive imaging for security and healthcare applications at 94 GHz and 120 GHz bands. Current research efforts include realization of compact low-power antenna array systems at mm-wave and sub-mm-waves with higher performance and more sophistication, e.g., including on-chip Built-In Self-Test (BIST), calibration, and integration with the Digital Signal Processing (DSP) core.
This short course covers the basics of multi-antenna systems, narrowband phased arrays, wideband timed arrays, transceiver architectures, circuit building blocks, and several case studies spanning 1 – 100 GHz for various applications.
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3D多媒體技術暨課程研討會 產學界多位博士教授 2012-11-17 09:30 電機二館105室
3D多媒體技術暨課程研討會 演講者:產學界多位博士教授|
時間:Date:2012-11-17|TIme:09:30
地點:電機二館105室
主辦單位:教育部智慧電子整合性人才培育計畫 4C電子聯盟中心
協辦單位:台灣大學系統晶片中心/台大電子所
聯絡人:邱玉霜
聯絡電話:02-33663718
演講內容:
3D多媒體多媒體技術暨課程研討會

三維電腦繪圖技術日益受到重視,在電腦遊戲之外,電腦繪圖技術更廣泛用於人機介面之應用,在泛用式繪圖處理器的發展之下,電腦繪圖的技術也將被應 用到各式多媒體信號處理及科學運算上,在近年來熱門的智慧行動裝置中,繪圖處理器也成為最重要的矽智財之一。

有鑑於此,教育部智慧電子整合性人才培育計畫 4C電子聯盟中心針對三維多維多媒體開發教材,以做中學的方式,讓修課的同學都能對三維電腦繪圖的基本原理、軟體平台、硬體架構有相當程度的了解,此研討 會為三維多維多媒體之課程發表會,會中將安排業界先進對於未來發展趨勢做說明,並由幾位參與教材開發的老師進行課程教學並進行專題的展示。此課程 適合對此領域以及教材有興趣的老師及學生們參與,也很適合對此題目有興趣的業界同仁參與。

報名費用:免費!
報名期間:至 2012/11/09
活動時間: 2012/11/17-18
活動地點:台灣大學電機二館
     105 會議室
報名方式:見以下網址(含交通方式)
http://media.ee.ntu.edu.tw/signup.php

本活動備有午餐及中場點心!

會議時程:

第一天 (11/17)
上午
    09:30--10:30 演講:Heterogeneous Computing Architecture and Multimedia Framework Trend for Smartphone (聯發科技梁柏嵩特助)
    10:30--10:50 Coffee break
    10:50--11:50 Introduction (
國立臺灣大學簡韶逸教授)
    Lunch
下午
    01:00--03:00 Graphics pipeline簡介 (國立清華大學李潤容教授)
    03:00--03:30 Graphics pipeline
專題成果展示 (TA)
    03:30--03:50 Coffee break
    03:50--05:50 Graphics library
簡介 (國立師範大學張鈞法教授)
    05:50--06:20 Graphics library
專題成果展示 (TA)

第二天 (11/18)
上午
    09:30--11:30 GPU hardware (國立臺灣大學簡韶逸教授&國立交通大學范倫達教授)
    11:30--11:50 Coffee break
    11:50--12:20 GPU hardware
專題成果展示 (TA)


聯絡人 :邱玉霜小姐 shuang@cc.ee.ntu.edu.tw (02)3366-3700#370
主辦單位:教育部智慧電子整合性人才培育計畫 4C電子聯盟中心
協辦單位:國立臺灣大學系統晶片中心
承辦單位:國立臺灣大學電子工程學研究所
教育部智慧電子整合性人才培育計畫 4C電子聯盟中心
附加檔案: Download
Automatic Error Localization and Correction for Simple Software Georg Hofferek 2012-11-13 15:30 133, EE2 Building
Automatic Error Localization and Correction for Simple Software 演講者:Georg Hofferek|Graz University of Technology
時間:Date:2012-11-13|TIme:15:30
地點:133, EE2 Building
主辦單位:GIEE
協辦單位:GIEE
聯絡人:Jie-Hong Jiang
聯絡電話:
演講內容:
Controller synthesis is the problem of finding Boolean functions that
correspond to correct-by-construction implementations of control signals
in digital systems. This corresponds to finding (Boolean) witness
functions in quantified second-order formula with a particular
quantifier structure. One of the ways to realize this is interpolation
in first-order theories, in particular the (quantifier-free fragment of
the) theory of uninterpreted functions and equality (QF_UF). Multiple
control signals can be computed at once, from a single proof, if the
proof meets certain criteria. These criteria, and ways to obtain proofs
that meet them, will be discussed.
 
附加檔案:
Automatic Error Localization and Correction for Simple Software Robert Koenighofer 2012-11-13 16:30 133, EE2 Building
Automatic Error Localization and Correction for Simple Software 演講者:Robert Koenighofer|Graz University of Technology
時間:Date:2012-11-13|TIme:16:30
地點:133, EE2 Building
主辦單位:GIEE
協辦單位:GIEE
聯絡人:Jie-Hong Jiang
聯絡電話:33663685
演講內容:
Debugging consists of three steps: error detection, localization, and
correction. While there exist many techniques to automate error
detection, the latter two steps are usually done manually. This talk
will present methods to automate them as well. We assume that the error
in the program is a faulty expression. For error localization, we
compute sets of faulty expressions that can be modified in such a way
that the program satisfies a given specification. For error correction,
we synthesize new versions of the faulty expressions using templates and
counterexample-guided refinements.
附加檔案:
Growth and application of quantum dot superlattice for high-efficiency intermediate band solar cells Prof. Yoshitaka Okada 2012-08-24 10:30 EE2-124
Growth and application of quantum dot superlattice for high-efficiency intermediate band solar cells 演講者:Prof. Yoshitaka Okada |The University of Tokyo Research Center for Advanced Science and Technology
時間:Date:2012-08-24|TIme:10:30
地點:EE2-124
主辦單位:電子所
協辦單位:電機系
聯絡人:林浩雄教授
聯絡電話:33663670
演講內容:
[Abstract]
    Effciency enhancements exceedingthe Shockley-Queisserlimit of a single junction solar cell is possible with an intermediate band solar cell(IBSC), which incorporates a quantum dot (QD) superlatticein the active region of a p-i-ncell structure. The presence of IB leads to generation of a net electron-hole pair when two below-bandgapphotons are absorbed, i.e.one photon pumps an electron from the valence band (VB) to IB, while a second photon pumps an electron from the IB to conduction band (CB). These electron-hole pairs add to those produced by band-to-band transitions with photons above the bandgapenergy that excite electrons directly from VB to CB.
   Experimental challenges to demonstrate IBSCs require fabrication of a close-packed QD superlattice. We have demonstrated the first QD solar cell with 30 multi-stacked InAs/AlGaInAsQD layers fabricated on InP(311)B substrate by using strain compensation technique. Recently, strain-compensation technique has been applied to demonstrate multi-stacked QDSCs with InAs/GaNAson GaAssubstrates.
附加檔案: Download
Part I: My Student Days and My Career at Bell Labs and University of California at Berkeley; Part II (30 min): Computer-Aided Design, Physical-Design and Interconnects for Signal Processing Ernest KuhProfessor 2012-07-04 16:00 博理201會議室
Part I: My Student Days and My Career at Bell Labs and University of California at Berkeley; Part II (30 min): Computer-Aided Design, Physical-Design and Interconnects for Signal Processing 演講者:Ernest KuhProfessor|
時間:Date:2012-07-04|TIme:16:00
地點:博理201會議室
主辦單位:電子所
協辦單位:
聯絡人:張耀文所長
聯絡電話:
演講內容:
講者:葛守仁院士(Professor Ernest Kuh), Professor Emeritus, University of California at Berkeley
           中研院院士, 美國國家工程學院院士
講題:Part I (30 min): My Student Days and My Career at Bell Labs and University of California at Berkeley
            Part II (30 min): Computer-Aided Design, Physical-Design and Interconnects for Signal Processing
時間:16:00 ─ 17:00
地點:博理201會議室
 
 

葛守仁院士Biography:

Professor Ernest Kuh attended Shanghai Jiao Tong University from 1945 to 1947; received the B.S. degree from the University of Michigan in 1949; the S.M. degree from the Massachusetts Institute of Technology in 1950; the Ph.D. degree from Stanford University in 1952; the Doctor of Engineering, Honoris Causa, Hong Kong University of Science and Technology in 1997; and the Doctor of Engineering degree from the National Chiao Tung University, Taiwan in 1999. He joined the EECS Department faculty in 1956. From 1968 to 1972 he served as chair of the department; from 1973 to 1980 he served as Dean of the College of Engineering. From 1952 to 1956 he was a member of the Technical Staff at Bell Telephone Laboratories in Murray Hill, New Jersey. Prof. Kuh is a member of the National Academy of Engineering, the Academia Sinica, and a foreign member of the Chinese Academy of Sciences. He is a Fellow of IEEE and AAAS. He has received numerous awards and honors, including the ASEE Lamme Medal, the IEEE Centennial Medal, the IEEE Education Medal, the IEEE Circuits and Systems Society Award, the IEEE Millennium Medal, the 1996 C&C Prize, and the 1998 EDAC Phil Kaufman Award.
Prof. Kuh has served on many academic advisory committees and boards, including those at the Massachusetts Institute of Technology, Princeton University, the University of Southern California, and the Hong Kong University of Science and Technology. He has been a consultant to a number of industrial and governmental organizations, including International Business Machines, General Motors, Cadence Design Systems, the National Science Foundation, and the National Institute of Standards and Technology. He was a member of the Board of Directors of the IEEE from 1976 to 1978 and served as President of the IEEE Circuits and Systems Society in 1972. He served as a board member of ECAD and Cadence Design. Currently, he is on the Board of Ultima Interconnect.
 

 
臺大電子所鼓勵學生參加演講活動101年7-12月集點辦法
1.      本活動參加對象:電子所在學同學。
2.      集點卡索取地點:電子所所辦和演講會場。
3.   集點卡限本人使用,姓名與學號一經寫定不得塗改。
4.      每次進場、離場均需核章,遲到或早退將不予核章,事後亦不予補章。(演講如提早結束請主動致電所辦通知,並請在現場等候核章)
5.      凡參加電子所主辦、協辦之課程外演講,於發送公告時有註明參加集點活動,均可累積點數,全程參與者,每次核發乙點。每張集點卡可累計3點,累計滿3點之集點卡即取得摸彩資格,可多參加演講活動累計多張集點卡以增加中獎機會,獎項將分兩大項,每位學生僅限得一項。
6.      凡累計滿3點之集點卡,請於102年1月4日(五)17:30前將集點卡投入所辦之摸彩箱,電子所將於102/1/7假榮譽頒獎典禮舉行公開抽獎。
7.      本次辦理期間為101年7月2日(一)~12月31日(一)。
附加檔案: Download
Architecting Computer Systems for the Die-Stacking Future Gabriel Loh Principal Researcher 2012-04-24 10:00 博理館201室
Architecting Computer Systems for the Die-Stacking Future 演講者:Gabriel Loh Principal Researcher|Advanced Micro Devices (AMD)
時間:Date:2012-04-24|TIme:10:00
地點:博理館201室
主辦單位:行政院國家科學委員會
協辦單位:臺大資工系所/臺大電子所
聯絡人:邱玉霜
聯絡電話:33663700#370
演講內容:
【演講資訊】邀請Dr. Gabriel Loh (Principal Researcher at AMD)蒞校演講:Architecting Computer Systems for the Die-Stacking Future
演講時間:2012.4.24星期二上午10:00~11:30
演講地點:臺大博理館201
演講者:Dr. Gabriel Loh (Principal Researcher at AMD)
演講主題:Architecting Computer Systems for the Die-Stacking Future
演講摘要:
Three-dimensional die-stacking technologies are rapidly maturing, with intense research and development happening in the areas of manufacturing, EDA/CAD, test and yield improvement.  Stacking DRAM with high-performance computing (e.g., multi-core CPUs, heterogeneous APUs) potentially provides benefits in terms of reduced memory latency, increased memory bandwidth, and reduced memory power.  To achieve the full potential of stacked DRAM, however, the stacked DRAM cannot be simply interfaced using traditional organizations.  In this talk, I will focus on possible directions for using stacked DRAM and the associated challenges, opportunities, and some possible solutions.  The talk will also cover other research problems related to die-stacked computer architectures beyond DRAM-stacking issues.
講者簡介:
Gabriel Loh is a Principal Researcher at Advanced Micro Devices (AMD).  Gabe received his PhD and MS in computer science from Yale University and his BE in electrical engineering from the Cooper Union.  Gabe was also a tenured associate professor in the College of Computing at the Georgia Institute of Technology, a visiting researcher at Microsoft Research, and a senior researcher at Intel Corporation. His research interests include computer architecture, processor microarchitecture, emerging technologies and 3D die stacking.  He is a senior member of IEEE and the ACM.
 
主辦單位:行政院國家科學委員會 協辦單位:臺大資工系所/臺大電子所
附加檔案: Download
Computational needs for a smarter grid: a data analytic, optimization, simulation perspective Dr. Jinjun Xiong 2012-01-19 10:30 BL-103
Computational needs for a smarter grid: a data analytic, optimization, simulation perspective 演講者:Dr. Jinjun Xiong|Manager and Research Staff Member at the IBM Thomas J. Watson Research Center
時間:Date:2012-01-19|TIme:10:30
地點:BL-103
主辦單位:電子所
協辦單位:Intel-NTU創新研究中心、國科會
聯絡人:陳少傑
聯絡電話:3366-3700#417
演講內容:
[Abstract]
 According to the US DOE publication, GridVision2030, the US Power grid, arguably the most complex machine ever built is aging, inefficient, congested and incapable of meeting the future needs of information economy. The current power grid was designed to handle the maximum peak capacity with graceful responses to the contingencies. However, the investment in the infrastructure has lagged far behind the increase in the energy demand, causing grids to operate much closer to their transfer limits. A new operating mode with the same standards of reliability requires significantly improved situational awareness of the grid. This presentation will explore the computational challenges in the context of the following three areas of smart grid analysis: security-constrained unit commitment and economic dispatch with stochastic analysis, massive data set management, and large scale grid simulation.
 
[Biography]
 Dr. JinjunXiongis a Manager and Research Staff Member at the IBM Thomas J. Watson Research Center, working in areas of electronic design automation, and smarter grid and smarter energy. He has published more than 60 technical papers in refereed international conferences and journals. He has also filed more than 20 U.S. and world-wide patents. He was the PI for the U.S. Department of Energy (DOE) Project, Request for Information on Computation Needs for the Next-Generation Electric Grid from 2010 to 2011. The project produced a special report, titled “Framework for large-scale modeling and simulation of electricity systems for planning, monitoring, and secure operations of next generation electricity grids.” He is a member of the IBM's smart energy research team, and one of the projects he is working on is the Pacific Northwest Smart Grid Demonstration Project, one of the largest U.S. DOE Smart Grid Demonstration projects.
附加檔案:
Introduction to SmartSpice, Silvaco Taiwan 杜啟平經理 2011-12-19 16:30 博理112
Introduction to SmartSpice, Silvaco Taiwan 演講者:杜啟平經理|Silvaco Taiwan
時間:Date:2011-12-19|TIme:16:30
地點:博理112
主辦單位:電子所
協辦單位:
聯絡人:陳信樹
聯絡電話:
演講內容:
SmartSpice is one SPICE simulator delivering high performance and accuracy
required to design complex high precision analog circuits, analog
mixed-signal circuits, analyze critical nets, characterize cell libraries,
etc.. SmartSpice is compatible with popular analog design flows and
foundry-supplied device models. Recently, it has become freely accessible to
the Taiwanese academia through National Chip Implementation Center (CIC).
附加檔案:
Emerging Trends In Analog Design, A little bit of Analog, awhole lot of Digital Prof. Bibhu Datta Sahoo 2011-12-14 15:00 EE2-142
Emerging Trends In Analog Design, A little bit of Analog, awhole lot of Digital 演講者:Prof. Bibhu Datta Sahoo|ndian Institute of Technology
時間:Date:2011-12-14|TIme:15:00
地點:EE2-142
主辦單位:電子所
協辦單位:臺大-聯發科技無線研究實驗室
聯絡人:李泰成
聯絡電話:
演講內容:
附加檔案:
Spin on Nano! Dr. Stuart Parkin 2011-12-05 15:20 BL113
Spin on Nano! 演講者:Dr. Stuart Parkin|
時間:Date:2011-12-05|TIme:15:20
地點:BL113
主辦單位:物理系
協辦單位:
聯絡人:林彥志助教
聯絡電話:
演講內容:
Abstract:
The spin of the electron strongly influences or even controls the state of matter in a wide variety of materials including ferromagnets, superconductors and antiferromagnetic Mott insulators. Subtle changes in structure or changes in external conditions such as temperature or pressure or, perhaps, more interestingly, from a technological perspective, current, electric field, or voltage can cause dramatic changes in properties of such spin-based materials, even phase transitions. I will discuss several examples of spin-based phenomena that lead to novel applications and nano-devices.
 
 
Biography:
Stuart Parkin is an IBM Fellow and Manager of the Magnetoelectronics group at the IBM Research - Almaden, San Jose, California and a consulting professor in the Department of Applied Physics at Stanford University. He is also director of the IBM-Stanford Spintronic Science and Applications Center, which was formed in 2004. In 2007 Dr. Parkin was named a Distinguished Visiting Professor at the National University of Singapore, a Visiting Chair Professor at the National Taiwan University, and an Honorary Visiting Professor at University College London, The United Kingdom. In 2008, he was elected to the National Academy of Sciences. The Materials Research Network Dresden granted him the Dresden Barkhausen Award 2009. Parkin has been awarded honorary doctorates by the University of Aachen, Germany and the Eindhoven University of Technology, The Netherlands. Parkin has authored more than 350 papers and has more than 60 issued patents.
附加檔案: Download
電腦作業之健康危害及預防-專題演講 林志威博士 2011-10-31 13:30 BL113
電腦作業之健康危害及預防-專題演講 演講者:林志威博士|職業醫學與工業衛生研究所
時間:Date:2011-10-31|TIme:13:30
地點:BL113
主辦單位:電子所
協辦單位:
聯絡人:張莉妤
聯絡電話:33663528
演講內容:
各位同學您好:
 
有關本週專題演講課程之主題及課程上課相關資訊,詳見附加檔案。
另外提醒,10/31上課日,上課地點於博理館113教室,需上課同學為碩士班單號同學與博士班全體同學。
 
注意事項:
1. 本課程由13:30開始,為尊重演講者,助教將於13:20點名完畢,並且13:30後不得進入教室。
超過13:20仍未就定位者,視同缺席,不接受任何理由,無故提前早退者,也視同缺席。
2. 請假規定:每週將寄發缺席名單(包括請假、曠課等)給所有同學及指導教授。
為確保各位同學之權益,若同學mail address更新,請務必向助教電子所辦更新,若出缺席有任何疑問,請盡快來信給助教。
附加檔案:
Property Directed Reachability Analysis Niklas Een (MiniSat author) 2011-10-07 15:00 Room 145, EE2 Building
Property Directed Reachability Analysis 演講者:Niklas Een (MiniSat author)|UC Berkeley
時間:Date:2011-10-07|TIme:15:00
地點:Room 145, EE2 Building
主辦單位:GIEE, National Taiwan University
協辦單位:
聯絡人:Jie-Hong Roland Jiang
聯絡電話:(02)33663685
演講內容:

Abstract:

Last spring, in March 2010, Aaron Bradley published the first truly new bit-level symbolic model checking algorithm since Ken McMillan’s interpolation based model checking procedure introduced in 2003. Our experience with the algorithm suggests that it is stronger than interpolation on industrial problems, and that it is an important algorithm to study further. In this paper, we present a simplified and faster implementation of Bradley’s procedure, and discuss our successful and unsuccessful attempts to improve it.

Bio:

Niklas finished his Ph.D. on SAT based formal verification in 2005, and has continued to work as a researcher, first at Cadence Berkeley Labs, and later at University of California, Berkeley. He is mostly known for co-authoring the SAT-solver MiniSat, but his interests also include hardware verification and logic synthesis. 

附加檔案:
Toward the Design of Robust and Self-Healing Memories Prof. Hsien-Hsin S. Lee 2011-10-05 14:00 電機二館105室
Toward the Design of Robust and Self-Healing Memories 演講者:Prof. Hsien-Hsin S. Lee|School of Electrical and Computer Engineering, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta
時間:Date:2011-10-05|TIme:14:00
地點:電機二館105室
主辦單位:行政院國家科學委員會 /台灣大學電子所
協辦單位:Intel-台灣大學創新研究中心
聯絡人:邱玉霜
聯絡電話:33663718
演講內容:
Abstract
A new class of memory called Storage Class Memory (SCM) is emerging to be considered an integral part of the main memory hierarchy. The salient features of these memory classes include non-volatility, MLC capability, better scalability, fast access speed, low supply voltage, and lower power without mechanical operations. Despite these prominent properties, their adoption is hindered by their operational reliability, primarily due to their low write endurance. The situation is exacerbated under the scenarios of deliberately designed malicious attacks. In this talk, I will discuss our recent research for improving their reliability via three architectural technologies: taper-proof wear-leveling, self-healing capability, and hybrid memory architecture with multi-dimensional address classification. The first approach aims at randomizing and obfuscating the write patterns of these memories with one additional level of address remapping within the memory module. The second method presents a novel multi-bit error recovery mechanism that can self-repair multi-bit stuck-at faults and continue to use these memories even if some cells become faulty and unusable. The third technique advocates a wearout-hardened memory architecture to enhance the reliability by including a small SRAM cache and a low-cost classification and allocation policy. With these techniques, we will be able to extend the lifetime of these SCM to approach the theoretical limit and even continue to operate them when faulty cells are present.
 
Speaker Bio
Dr. Hsien-Hsin S. Lee is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology. He has a Ph.D. degree in Computer Science and Engineering from the University of Michigan, Ann Arbor. His current research interests include computer architecture, memory hierarchy, low-power VLSI, cyber security, and 3D-IC technology. Prior to joining Georgia Tech in 2002, he spent 6 years as a senior processor architect and a research staff member at Intel Corporation designing Pentium III processor and conducted research for Itanium architecture and one year at Agere Systems as an architecture manager for their StarCore DSP proliferations. Dr. Lee has received the Horace H. Rackham Distinguished Dissertation Award from the University of Michigan, an NSF CAREER Award, a Department of Energy Early CAREER Award, and the Georgia Tech ECE Outstanding Jr. Faculty Award, and the IBM Faculty Award. He had co-authored 3 papers that won Best Paper Awards, one paper selected in 2010 IEEE MICRO Top Picks, and holds 4 U.S. patents. He is a senior member of both the ACM and the IEEE.
 
免費入場,歡迎提早入場!
附加檔案:
Technology Trends and Implications on SoC Design Dr. Jeffrey L. Burns 2011-09-27 9:30 BL215
Technology Trends and Implications on SoC Design 演講者:Dr. Jeffrey L. Burns|IBM T.J. Watson Research Center
時間:Date:2011-09-27|TIme:9:30
地點:BL215
主辦單位:電子所
協辦單位:電機系
聯絡人:陳少傑
聯絡電話:
演講內容:
附加檔案:
Floorplanning Challenges in Early Chip Planning Dr. Jeonghee Shin 2011-09-27 10:30 BL215
Floorplanning Challenges in Early Chip Planning 演講者:Dr. Jeonghee Shin|IBM T.J. Watson Research Center
時間:Date:2011-09-27|TIme:10:30
地點:BL215
主辦單位:電子所
協辦單位:電機系
聯絡人:陳少傑
聯絡電話:
演講內容:
附加檔案:
The Pending Arrival of Phase Change Memory: The Implications on the Memory-Storage Hierarchy and on Future Systems Development Dr. Stefanie Chiras 2011-09-27 11:30 BL215
The Pending Arrival of Phase Change Memory: The Implications on the Memory-Storage Hierarchy and on Future Systems Development 演講者:Dr. Stefanie Chiras|IBM Austin Research Lab.
時間:Date:2011-09-27|TIme:11:30
地點:BL215
主辦單位:電子所
協辦單位:電機系
聯絡人:陳少傑
聯絡電話:
演講內容:
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The Future of Microprocessor Prof. Yale N. Patt 2011-09-26 15:30 明達231
The Future of Microprocessor 演講者:Prof. Yale N. Patt |UT Austin, USA
時間:Date:2011-09-26|TIme:15:30
地點:明達231
主辦單位:電子所
協辦單位:電機系
聯絡人:陳少傑
聯絡電話:
演講內容:
附加檔案:
Nanosystems: technologies and architectures for sensing and computing Prof. Giovanni DeMicheli 2011-09-26 15:30 BL112
Nanosystems: technologies and architectures for sensing and computing 演講者:Prof. Giovanni DeMicheli|EPF Lausanne, Switzerland
時間:Date:2011-09-26|TIme:15:30
地點:BL112
主辦單位:電子所
協辦單位:電機系
聯絡人:陳少傑
聯絡電話:
演講內容:
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FinFET-3D Transistor for 2011 and Beyond Prof. Chenming HuTSMC Chair Professor 2011-08-01 14:00 博理館201室
FinFET-3D Transistor for 2011 and Beyond 演講者:Prof. Chenming HuTSMC Chair Professor|UC Berkeley
時間:Date:2011-08-01|TIme:14:00
地點:博理館201室
主辦單位:電子所
協辦單位:
聯絡人:吳依倩
聯絡電話:33663529
演講內容:
以下演講有配合電子所參加演講集點活動,現場核發集點卡,全程參加可核章集點,
已領有集點卡的同學,請記得攜帶您的集點卡來核章!
 

 
胡正明教授為電子所特聘研究講座,本次活動除邀請胡教授演講之外, 尚有師生座談活動:
14:00~15:30 演講 @BL201
15:30~16:30 與學生座談 @BL201
16:30~17:30 與教師交流 @BL302
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[新創漫談] 基於新技術創業的挑戰–MIT見聞分享 邱大剛執行長 2011-06-17 17:30 電機二館142會議室
[新創漫談] 基於新技術創業的挑戰–MIT見聞分享 演講者:邱大剛執行長|現觀科技
時間:Date:2011-06-17|TIme:17:30
地點:電機二館142會議室
主辦單位:臺大電子所
協辦單位:臺大系統晶片中心
聯絡人:劉宜汶
聯絡電話:02-33669909
演講內容:
新創漫談系列座談
「基於新技術創業的挑戰– MIT見聞分享」
 
常常聽台大同學聊起對未來的職涯規畫與想像,大多數優異的台大同學們認為畢業後進入著名的上市上櫃公司是唯一且必要的道路。這條「從名校通往大公司」的路聽起來固然很合理,但在這個安穩的選擇以外,資賦優異的台大人,其實有能力接受更大的挑戰,值得更開闊、更驚奇的未來!
 
Groundhog Technologies(現觀科技)創辦人暨執行長邱大剛,為MIT Media Lab(麻省理工學院多媒體實驗室)碩士,曾獲選Merrill Lynch Fellow。台大電機系98級,期間曾獲選大專優秀青年及多項工程獎項,也曾於at&t Labs-Research 擔任研究助理。他是八項專利的發明人,另有十一項專利申請中。
 
現觀科技是全球第一個基於使用者行為模式的計算而優化無線通訊網路的公司,以此獨特技術協助美國at&t、Sprint,日本三大業者、中國移動、中華電信等電信業者解決許多棘手的問題,至今仍居此利基市場的第一名。現觀科技也在2009年被美國Red Herring 雜誌選為全球前兩百強的新創科技公司。
 
由於邱大剛在科技界年輕一代的影響力,他曾代表台灣參與一些國際活動,例如Asia 21 Young Leaders Summit、Europe-Asia Young Leaders' Forum、2003 Asia Pacific Innovation and Entrepreneurship Conference, WYPS of United Nations,他也是工研院創意中心的顧問。
 
有句話說:「想像力是你的超能力!」優秀的台大學生對於未來的職涯之路也應該充滿「想像力」。相信「新創漫談」可以為各位同學帶來「想像」的力量、以及「超能」的勇氣!請留下星期四傍晚與空腹,在享受美食的同時,聆聽傑出學長娓娓道出他的心路歷程,及學習他的人生智慧!
 
台大系統晶片中心與台大電子所 敬邀
 
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[Invited Talk] Non-Self-Jamming Millimeter-Sized Radio-Frequency Identification Prof. Edwin C. Kan 2011-05-24 09:30 博理館201室
[Invited Talk] Non-Self-Jamming Millimeter-Sized Radio-Frequency Identification 演講者:Prof. Edwin C. Kan|College of ECE, Cornell
時間:Date:2011-05-24|TIme:09:30
地點:博理館201室
主辦單位:電機系
協辦單位:
聯絡人:林清富教授
聯絡電話:
演講內容:
Non-Self-Jamming Millimeter-Sized Radio-Frequency Identification
Abstract :
Reliable and miniature passive RFID is an important component in many local sensor network and biomedical applications. To reduce the antenna size, higher frequency in the high GHz band has to be employed. Self interference has also been a serious problem. We present a new RFID system based on efficient harmonic generation of the nonlinear transmission lines (NLTL). Because the backscattered signal is at the second or third harmonics of the fundamental interrogating frequency, self jamming from readers and multi-path reflection are eliminated. Matched NLTL with dual antennas and reflective NLTL with single antenna on the RFID tag will be investigated for efficiency comparison. We will present the full RFID system, smaller than 1mm3 with antennas, and the associated ASK/BPSK data modulation and sensor integration schemes. This new NLTL system is the smallest passive RFID with the longest range to date. 
Based on similar NLTL structures with the same form factors including antenna, we can also construct active RF systems with 2µW budget for ranges up to 1km. The design principle of efficient power conversion to the Bragg oscillation frequency and control of the ultra-wide-band impulse radio (UWB-IR) will be introduced on the NLTL system.  This active radio option can supplement the RFID components for a full, versatile network configuration.
 
Biography:
Edwin Chihchuan Kan received the B.S. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 1984, and the M.S. and Ph.D. degrees from the University of Illinois, Urbana, in 1988 and 1992, respectively, all in electrical engineering. In January 1992, he joined Dawn Technologies as a Principal CAD Engineer developing advanced electronic and optical device simulators and technology CAD framework. He was then with Stanford University, as a Research Associate from 1994 to 1997. From 1997 to 2002, he was an Assistant Professor with the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, where he is now a Professor and Director of Graduate Studies. He has spent the summers of 2000 and 2001 at IBM Microelectronics, Yorktown Heights and Fishkill, NY, in the Faculty Partner Program. In 2004 and 2005, he has been a visiting researcher at Intel Research, Santa Clara, CA, and a visiting professor at Stanford University during his sabbatical leave. His main research areas include CMOS technology, semiconductor device physics, flash memory, CMOS biosensors, ultra-low power radio link, technology CAD, and numerical methods for PDE and ODE.
附加檔案:
[Invited Talk] CMOS Biosensing: Lots of Problems, Lots of Opportunities Prof. Edwin C. Kan 2011-05-24 14:45 博理館201室
[Invited Talk] CMOS Biosensing: Lots of Problems, Lots of Opportunities 演講者:Prof. Edwin C. Kan|College of ECE, Cornell
時間:Date:2011-05-24|TIme:14:45
地點:博理館201室
主辦單位:電機系
協辦單位:
聯絡人:林清富教授
聯絡電話:
演講內容:
Abstract :
With mass production fast marching to 22nm CMOS technology and beyond, we are approaching the information resolution of the biological systems such as DNA and ion channels. The close proximity of CMOS sensing, amplification, data conversion and transmission enables cost reduction and least noise injection. On the one hand, many exciting applications can be perceived based on never-before accessible biological and biomedical information, but on the other hand, many aspects of fundamental understanding on CMOS interface with bio-molecules and cells are still lacking.   Conventional ion-sensitive FET (ISFET) and microelectrode array (MEA) also face severe challenges in reliable operations and invasiveness reduction. 
This talk will present the device operations of chemoreceptive MOS (CnMOS) for monitoring ions, biomarker proteins, specific pathogen DNA, cellular action potentials and exocytosis.  Modeling of the surface layers with steric effects and reference electrodes will be investigated in detail to illustrate different modes of sensing and actuation.  We will also present benchmark transient and impedospectropic measurements on biomarkers, pathogens, neurotransmitters, A431 and hela cancer cells, mast cells and chromaffin cells with associated signal processing for reliable long-term data collection.  Future directions in co-location of electrochemical and optical sensors and in automonous system integration of sensor, sample/control circuits, power scavenging and wireless communication will be briefly summarized.
 
Biography:
Edwin Chihchuan Kan received the B.S. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 1984, and the M.S. and Ph.D. degrees from the University of Illinois, Urbana, in 1988 and 1992, respectively, all in electrical engineering. In January 1992, he joined Dawn Technologies as a Principal CAD Engineer developing advanced electronic and optical device simulators and technology CAD framework. He was then with Stanford University, as a Research Associate from 1994 to 1997. From 1997 to 2002, he was an Assistant Professor with the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, where he is now a Professor and Director of Graduate Studies. He has spent the summers of 2000 and 2001 at IBM Microelectronics, Yorktown Heights and Fishkill, NY, in the Faculty Partner Program. In 2004 and 2005, he has been a visiting researcher at Intel Research, Santa Clara, CA, and a visiting professor at Stanford University during his sabbatical leave. His main research areas include CMOS technology, semiconductor device physics, flash memory, CMOS biosensors, ultra-low power radio link, technology CAD, and numerical methods for PDE and ODE.
附加檔案:
[創意創業論壇] 創業新美學 科技X藝術X創業 黃心健 2011-05-16 17:30 霖澤館國際會議廳
[創意創業論壇] 創業新美學 科技X藝術X創業 演講者:黃心健|
時間:Date:2011-05-16|TIme:17:30
地點:霖澤館國際會議廳
主辦單位:臺大創意創業學程
協辦單位:臺大法律學院、臺大新聞研究所
聯絡人:鄭小姐
聯絡電話:02-33661462
演講內容:
5月16日創意創業論壇暨招生說明會,將請來藝術與科技跨領域達人黃心健,告訴你如何連結人生中的創意元素,勇敢踏出常規外的第一步,邁向實踐夢想的旅程!
 
論壇名稱:創業新美學  科技X藝術X創業
時間:2011.05.16()17:30開始入場18:00開講
地點:霖澤館國際會議廳
討論講題:聽花博夢想館設計者黃心健分享探索夢想勇敢創業的旅程
講者:黃心健
      世博台北館&花博夢想館設計者
     【天工開物】&【故事巢】創辦人
主持人:彭文正
        台大新聞研究所副教授
報名資訊:即日起開放網路報名  會前備有精緻餐點
          請上http://www.cep.ntu.edu.tw
 
講者介紹:
從高雄世運會、世博台北館到花博夢想館暨流行館,作品屢屢在國際性大型場合成為發光亮點的黃心健,由台大機械系畢業,卻投身工業設計領域,
到美國巴沙迪娜藝術中心學院工業設計系讀碩士,並成為伊利諾理工學院設計系博士候選人。由於同時具有科技與藝文背景,在美國分別受聘於Sega
研發部藝術總監及美國Sony電腦娛樂產品研發部藝術總監。2004年,黃心健回到國內發展,現在則是天工開物(Techart)&故事巢創辦人暨創意總監。
跨界整合,創意人生,從小喜歡拆手錶與畫漫畫,結合機械、藝術兩項天賦及興趣的黃心健,正符合了目前趨勢所急迫需求的人才類型。
 
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[電子所專題演講]Data–Based Mechanistic Modelling and the Scientific Method Dr. C. James Taylor 2011-05-16 13:30 博理館113室
[電子所專題演講]Data–Based Mechanistic Modelling and the Scientific Method 演講者:Dr. C. James Taylor| Lancaster University
時間:Date:2011-05-16|TIme:13:30
地點:博理館113室
主辦單位:臺大電子所
協辦單位:
聯絡人:吳小姐
聯絡電話:33663528
演講內容:
The speaker is a Senior Lecturer (Associate Professor) and Director of Teaching for Engineering at Lancaster University, United Kingdom. His research encompasses control system design, optimisation and time series analysis, with applications in robotics, electronics and the environment. He is on sabbatical leave as a visiting scholar at National Taiwan University until September 2011.
附加檔案:
[電子所專題演講]Techincal Paper Writing for Peer Reviewing 林守德教授 2011-05-09 13:20 博理館113室
[電子所專題演講]Techincal Paper Writing for Peer Reviewing 演講者:林守德教授|台大資工系
時間:Date:2011-05-09|TIme:13:20
地點:博理館113室
主辦單位:臺大電子所
協辦單位:
聯絡人:吳小姐
聯絡電話:33663528
演講內容:
附加檔案:
[光電所演講] 從生活壓力到生命活力 張純吉臨床心理師 2011-05-06 15:30 博理館101演講廳
[光電所演講] 從生活壓力到生命活力 演講者:張純吉臨床心理師|
時間:Date:2011-05-06|TIme:15:30
地點:博理館101演講廳
主辦單位:光電所
協辦單位:
聯絡人:姚小姐
聯絡電話:02-33663587
演講內容:
附加檔案:
A 32nm 0.5V-Supply Dual-Read High-Speed 6T SRAM 鄺仁德博士 2011-05-03 14:20 博理館113室
A 32nm 0.5V-Supply Dual-Read High-Speed 6T SRAM 演講者:鄺仁德博士|IBM Austin Research Lab
時間:Date:2011-05-03|TIme:14:20
地點:博理館113室
主辦單位:電子所
協辦單位:
聯絡人:呂學士教授
聯絡電話:
演講內容:
 
以下演講有配合電子所參加演講集點活動,現場核發集點卡,全程參加可核章集點,
已領有集點卡的同學,請記得攜帶您的集點卡來核章!
 

演講摘要:
Dual read port 6-transistor (6T) SRAMs play a critical role in high performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low voltage operation. In this talk, we will present a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle read and write access latency. The chip is designed and fabricated in a 32nm metal-gate partially depleted (PD) SOI process technology for low supply voltage scalability and low power applications. Hardware exhibits a robust operation at 348MHz and 0.5V with a read and write power of 3.33 and 1.97mW, respectively, per 4.5KB active array when both read ports are accessed at the highest switching activity data pattern. At a 0.6V supply, an access speed of 1.2GHz is observed at a reference performance level of 4+ GHz for a 1V supply.
 

 
臺大電子所鼓勵學生參加演講活動100年1-6月集點辦法
1.      本活動參加對象:電子所在學同學。
2.      集點卡索取地點:電子所所辦和演講會場。
3.   集點卡限本人使用,姓名與學號一經寫定不得塗改。
4.      每次進場、離場均需核章,遲到或早退將不予核章,事後亦不予補章。
5.      凡參加電子所主辦、協辦之課程外演講,均可累積點數,全程參與者,每次核發乙點。每張集點卡可累計3點,累計滿3點之集點卡即取得摸彩資格,可多參加演講活動累計多張集點卡以增加中獎機會,相關獎項如附件。每位學生頭獎和貳獎限得乙獎。
6.      凡累計滿3點之集點卡,請於100年6月30日(四)下班前前將集點卡投入所辦之摸彩箱,電子所將於7月初擇日舉行公開抽獎(詳細時間地點將於公告5月底前公告),不在場者視同棄權。
7.      本次辦理期間為100年1月3日(一)~6月30日(四)。
 
附件
頭獎   iPad 一名 (或價值約NT$15,000之等值獎項)
貳獎   數位相機一台(價值約NT$7,500)
参獎   金石堂圖書禮券NT$300 若干名
 
附加檔案:
[Intel - 臺大創新研究中心演講]Wireless Communication Networks in Extreme Environments : Trends and Challenges Prof. Winston K.G. Seah 2011-04-29 14:20 德田館101室(資工系)
[Intel - 臺大創新研究中心演講]Wireless Communication Networks in Extreme Environments : Trends and Challenges 演講者:Prof. Winston K.G. Seah|Victoria University of Wellington, New Zealand
時間:Date:2011-04-29|TIme:14:20
地點:德田館101室(資工系)
主辦單位:Intel-臺大創新研究中心、臺大資訊工程系
協辦單位:
聯絡人:李紫菱小姐
聯絡電話:33661468
演講內容:
Abstract:
The use of wireless communications is swiftly extending beyond networks for
the average person to networks for embedded devices, sensors and autonomous
systems, as well as networks for personnel in extreme environments—
underground, underwater and in disaster situations. Many existing wireless
networking technologies have been designed to handle conditions presented by
such environments and may not operate up to expectations. Some may even fail
totally. This lecture discusses the challenges of designing robust wireless
networks for communications in these extreme environments as well as issues
to be addressed in order for research to be implemented and deployed in a
realistic environment.

Short-bio:
Winston K.G. Seah received the Dr.Eng. degree from Kyoto University, Kyoto,
Japan, in 1997. He is currently Professor of Network Engineering in the
School of Engineering and Computer Science, Victoria University of
Wellington, New Zealand. Prior to this, he has worked for more than 16 years
in mission-oriented research, taking ideas from theory to prototypes, most
recently, as a Senior Scientist (Networking Protocols) in the Institute for
Infocomm Research (I2R), Singapore. He is actively involved in research in
the areas of mobile ad hoc and sensor networks, and co-developed one of the
first Quality of Service (QoS) models for mobile ad hoc networks. His latest
research interests include wireless sensor networks powered by ambient
energy harvesting (WSN-HEAP), wireless multi-hop networks, and
mobility-enhanced protocols and algorithms for networked swarm robotics and
sensing applications in terrestrial and oceanographic networks. He is a
Senior Member of the IEEE.
 
附加檔案:
[新創漫談] 晶睿通訊創立及成長分享 陳文昌董事長 2011-04-28 17:30 電機二館142會議室
[新創漫談] 晶睿通訊創立及成長分享 演講者:陳文昌董事長|晶睿通訊
時間:Date:2011-04-28|TIme:17:30
地點:電機二館142會議室
主辦單位:電子所
協辦單位:SOC中心
聯絡人:劉小姐
聯絡電話:33669909
演講內容:
新創漫談系列座談-
晶睿通訊創立及成長分享
 
常常聽台大同學聊起對未來的職涯規畫與想像,大多數優異的台大同學們認為畢業後進入著名的上市上櫃公司是唯一且必要的道路。這條「從名校通往大公司」的路聽起來固然很合理,但在這個安穩的選擇以外,資賦優異的台大人,其實有能力接受更大的挑戰,值得更開闊、更驚奇的未來!
 
本次創新漫談講座邀請了晶睿通訊股份有限公司董事長、同時擔任睿緻科技股份有限公司總經理的陳文昌學長和學弟妹分享「柳暗花明又一村」的創業經驗。陳文昌學長是勤奮踏實的蘭陽子弟。在創業前曾擔任交通部電信研究所副研究員、連宇股份有限公司研發部經理。然而他不甘於平順的職業生涯,十年前他毅然決然離開安穩的跑道,除了重返校園至台大電機所攻讀博士,更和一群志趣相投的學弟、妹共同創業,成立晶睿通訊股份有限公司。
 
創業初期,陳文昌學長的創業團隊將晶睿的定位放在「技術代工」上,但卻也因此在第一年慘賠一千多萬,幾乎損失半個資本額。然而陳文昌學長並沒有因此受挫,反而發揮膽識,看準「網路」是未來大勢所趨,捨棄原本熟悉的視訊會議產業和類比式攝影機產業領域,開始將事業觸角伸向網路安全監控領域。這條當時仍「人煙稀少的路」,卻也帶著他們通往「柳暗花明」的事業與商機,不但讓晶睿轉虧為盈,於民國95年順利成為上櫃公司,還創造現今驚人的營運績效和至今雄踞於前的市場排名!
 
   有句話說:「想像力是你的超能力!」優秀的台大學生對於未來的職涯之路也應該充滿「想像力」。相信「新創漫談」可以為各位同學帶來「想像」的力量、以及「超能」的勇氣!
     請留下星期四傍晚與空腹,再享受Pizza與美食的同時,聆聽傑出學長娓娓道出他的心路歷程,及學習他的人生智慧!
 
 
臺大系統晶片中心與臺大電子所 敬邀
 
本活動採網路報名
 
附加檔案:
Sustainable Silicon:Energy-Efficient VLSI Interconnects Prof. Patrick Chiang 2011-04-28 09:30 電機二館105視聽教室
Sustainable Silicon:Energy-Efficient VLSI Interconnects 演講者:Prof. Patrick Chiang|Oregon State University, USA
時間:Date:2011-04-28|TIme:09:30
地點:電機二館105視聽教室
主辦單位:電機系/電子所
協辦單位:IEEE SSCS Taipei Chapter
聯絡人:陳信樹教授
聯絡電話:33663700#246
演講內容:
以下演講有配合電子所參加演講集點活動,現場核發集點卡,全程參加可核章集點,
已領有集點卡的同學,請記得攜帶您的集點卡來核章!

主題:Sustainable Silicon:Energy-Efficient VLSI Interconnects
講者:Prof. Patrick Chiang, Oregon State University, USA
時間:100年4月28日(星期四) 上午9:30-10:30
地點:台灣大學電機二館105視聽教室


 
臺大電子所鼓勵學生參加演講活動100年1-6月集點辦法
1.      本活動參加對象:電子所在學同學。
2.      集點卡索取地點:電子所所辦和演講會場。
3.   集點卡限本人使用,姓名與學號一經寫定不得塗改。
4.      每次進場、離場均需核章,遲到或早退將不予核章,事後亦不予補章。
5.      凡參加電子所主辦、協辦之課程外演講,均可累積點數,全程參與者,每次核發乙點。每張集點卡可累計3點,累計滿3點之集點卡即取得摸彩資格,可多參加演講活動累計多張集點卡以增加中獎機會,相關獎項如附件。每位學生頭獎和貳獎限得乙獎。
6.      凡累計滿3點之集點卡,請於100年6月30日(四)下班前前將集點卡投入所辦之摸彩箱,電子所將於7月初擇日舉行公開抽獎(詳細時間地點將於公告5月底前公告),不在場者視同棄權。
7.      本次辦理期間為100年1月3日(一)~6月30日(四)。
 
附件
頭獎   iPad 一名 (或價值約NT$15,000之等值獎項)
貳獎   數位相機一台(價值約NT$7,500)
参獎   金石堂圖書禮券NT$300 若干名
附加檔案:
RRAM—An Emerging Non-volatile Memory Technology 劉明博士 2011-04-27 16:00 電機二館133教室
RRAM—An Emerging Non-volatile Memory Technology 演講者:劉明博士|中國科學院
時間:Date:2011-04-27|TIme:16:00
地點:電機二館133教室
主辦單位:電子所(劉致為教授)
協辦單位:
聯絡人:胡小姐
聯絡電話:33663700#421
演講內容:
以下演講有配合電子所參加演講集點活動,現場核發集點卡,全程參加可核章集點,
已領有集點卡的同學,請記得攜帶您的集點卡來核章!
 

 
 

臺大電子所鼓勵學生參加演講活動100年1-6月集點辦法
1.      本活動參加對象:電子所在學同學。
2.      集點卡索取地點:電子所所辦和演講會場。
3.   集點卡限本人使用,姓名與學號一經寫定不得塗改。
4.      每次進場、離場均需核章,遲到或早退將不予核章,事後亦不予補章。
5.      凡參加電子所主辦、協辦之課程外演講,均可累積點數,全程參與者,每次核發乙點。每張集點卡可累計3點,累計滿3點之集點卡即取得摸彩資格,可多參加演講活動累計多張集點卡以增加中獎機會,相關獎項如附件。每位學生頭獎和貳獎限得乙獎。
6.      凡累計滿3點之集點卡,請於100年6月30日(四)下班前前將集點卡投入所辦之摸彩箱,電子所將於7月初擇日舉行公開抽獎(詳細時間地點將於公告5月底前公告),不在場者視同棄權。
7.      本次辦理期間為100年1月3日(一)~6月30日(四)。
 
附件
頭獎   iPad 一名 (或價值約NT$15,000之等值獎項)
貳獎   數位相機一台(價值約NT$7,500)
参獎   金石堂圖書禮券NT$300 若干名
 
附加檔案:
Key Learning from Observing Highly Successful People 王文漢副總裁 2011-04-25 13:30 BL113
Key Learning from Observing Highly Successful People 演講者:王文漢副總裁|Intel-臺大創新研究中心
時間:Date:2011-04-25|TIme:13:30
地點:BL113
主辦單位:臺大電子所
協辦單位:Intel-臺大創新研究中心
聯絡人:吳小姐
聯絡電話:33663528
演講內容:
附加檔案: Download
Advanced On-Chip ESD Protection Design in CMOS Integrated Circuits 柯明道副校長 2011-04-18 2011-4-12 博理館101室
Advanced On-Chip ESD Protection Design in CMOS Integrated Circuits 演講者:柯明道副校長|義守大學
時間:Date:2011-04-18|TIme:2011-4-12
地點:博理館101室
主辦單位:臺大電子所
協辦單位:
聯絡人:吳小姐
聯絡電話:
演講內容:
柯副校長簡歷:
 
                  柯明道
                  交通大學電子研究所 特聘教授
                  義守大學 講座教授兼研究副校長
                  晶片系統國家型科技計畫 執行長(2010 Feb. ~ 2011 May)
                  奈米國家型科技計畫 執行長(2011 Jan. ~ )
                  IEEE Fellow (2008)
                  柯明道 於1993 年獲得國立交通大學電子研究所博士學位。曾經工作
                  於工研院電通所積體電路技術組,歷經工程師、課長、副理、以及部門經
                  理等職務,並曾榮獲工業技術研究院『研究成就獎 ─ 個人獎』。柯教授於
                  1999 年9 月加入交通大學電子工程學系擔任助理教授,歷經副教授與正教
                  授之升等審查,於2004 年8 月升等為正教授,並於2010 年獲選為交通大
                  學特聘教授。柯教授在積體電路與微電子系統之可靠度設計技術領域已累
                  積豐碩之研究成果,多年來累計已發表國際學術期刊/研討會論文超過400
                  篇。累計已獲證美國專利177 件,以及中華民國專利153 件。
                  柯教授曾獲國際電機電子工程師學會(IEEE) 電路與系統分會(IEEE
                  Circuits and Systems Society) 以及電子元件分會(IEEE Electron Devices
                  Society)挑選為年度傑出講座(Distinguished Lecturer),並於2008 年獲頒
                 『IEEE Fellow (院士)』學術殊榮。柯教授所研發的專利技術曾榮獲經濟部
                  94 年『國家發明創作獎』。柯教授曾獲選為中華民國第四十一屆(2003 年)
                 『十大傑出青年』,並於2009 年獲選為台灣『十大傑出發明家』,獲中國電
                   機工程師學會頒贈『傑出電機工程教授』獎,以及獲中國工程師學會頒贈
                 『傑出工程教授』獎。
                   於2008 年8 月,柯教授受命於交通大學吳校長任務指派,借調到義守
                   大學擔任講座教授兼研究副校長(現任中),協助推動交通大學與義联集團之
                   合作。
附加檔案: Download
[學術漫談] 「光電科技! 電機系...? and ...虛擬光學??」 曾雪峰教授 2011-03-29 17:30 電二142會議室
[學術漫談] 「光電科技! 電機系...? and ...虛擬光學??」 演講者:曾雪峰教授|光電所
時間:Date:2011-03-29|TIme:17:30
地點:電二142會議室
主辦單位:電子所
協辦單位:SOC中心
聯絡人:翁博軒
聯絡電話:poshuanweng@gmail.com
演講內容:
附加檔案:
[新創漫談] Startup Company: An Alternative Career Path 林珩之總經理 2011-03-24 17:30 電二142會議室
[新創漫談] Startup Company: An Alternative Career Path 演講者:林珩之總經理|T-Rich新創公司
時間:Date:2011-03-24|TIme:17:30
地點:電二142會議室
主辦單位:電子所
協辦單位:SOC中心
聯絡人:歐小姐
聯絡電話:02-33663531
演講內容:
附加檔案:
[Intel - 臺大創新研究中心演講] Design Challenges of Multi-Standard Radios on Scaled CMOS 傅昶綜博士 2011-03-24 10:30 電二146室
[Intel - 臺大創新研究中心演講] Design Challenges of Multi-Standard Radios on Scaled CMOS 演講者:傅昶綜博士|Intel Labs
時間:Date:2011-03-24|TIme:10:30
地點:電二146室
主辦單位:Intel-臺大創新研究中心
協辦單位::臺大電資學院、臺大電機系、臺大電子所
聯絡人:李紫菱小姐
聯絡電話:02-33661468
演講內容:
 
以下演講有配合電子所參加演講集點活動,現場核發集點卡,全程參加可核章集點,
已領有集點卡的同學,請記得攜帶您的集點卡來核章!

 
 

 
【臺大電子所鼓勵學生參加演講活動100年1-6月集點辦法】
1. 本活動參加對象:電子所在學同學。
2. 集點卡索取地點:電子所所辦和演講會場。
3. 集點卡限本人使用,姓名與學號一經寫定不得塗改。
4. 每次進場、離場均需核章,遲到或早退將不予核章,事後亦不予補章。
5. 凡參加電子所主辦、協辦之課程外演講,均可累積點數,全程參與者,每次核發乙點。每張集點卡可累計3點,累計滿3點之集點卡即取得摸彩資格,可多參加演講活動累計多張集點卡以增加中獎機會,相關獎項如附件。每位學生頭獎和貳獎限得乙獎。
6. 凡累計滿3點之集點卡,請於100年6月30日(四)下班前前將集點卡投入所辦之摸彩箱,電子所將於7月初擇日舉行公開抽獎(詳細時間地點將於公告5月底前公告),不在場者視同棄權。
7. 本次辦理期間為100年1月3日(一)~6月30日(四)。
 
《附件》
頭獎   iPad 一名 (或價值約NT$15,000之等值獎項)
貳獎   數位相機一台(價值約NT$7,500)
参獎   金石堂圖書禮券NT$300 若干名
附加檔案:
[生醫電資所演講] 3/21譚慶鼎教授(臺大醫學院耳鼻喉科) 譚慶鼎教授 2011-03-21 15:30 明達205室
[生醫電資所演講] 3/21譚慶鼎教授(臺大醫學院耳鼻喉科) 演講者:譚慶鼎教授|臺大醫學院耳鼻喉科
時間:Date:2011-03-21|TIme:15:30
地點:明達205室
主辦單位:生醫電資所
協辦單位:
聯絡人:曾小姐
聯絡電話:02-33664961
演講內容:
附加檔案:
[電子所專題演講] 3/21中研院黃鍔院士: My pilgrimage to Data Analysis 黃鍔院士 2011-03-21 13:30 博理101演講廳
[電子所專題演講] 3/21中研院黃鍔院士: My pilgrimage to Data Analysis 演講者:黃鍔院士|中央研究院
時間:Date:2011-03-21|TIme:13:30
地點:博理101演講廳
主辦單位:電子所
協辦單位:
聯絡人:吳嘉珍小姐
聯絡電話:02-33663528
演講內容:

【電子所專題演講(Department Colloquium)公告】

電子所將於3月21日(一)邀請中央研究院的黃鍔院士至本所演講:
  演講主題:My Pilgrimage to Data Analysis
        演講者 :黃鍔院士(中研院)
        演講日期:3月21日(一)
          時間:13:30-15:00
          地點:博理館101演講廳

黃鍔院士之簡歷:
黃鍔院士現職為國立中央大學國鼎講座教授暨數據分析方法研究中心主任,同時也是台灣中央研究院第二十五屆院士及美國工程研究院院士。黃鍔院士於1967年獲得約翰霍普金斯大學流體力學與數學博士學位,隨後曾任華盛頓大學海洋地理系研究員、北卡羅來納州立大學海洋地理學系副教授。1975年黃鍔院士進入美國航空暨太空總署工作30多年,並因其顯著研究成果榮獲許多獎項。

黃鍔院士過去主要研究領域為非線性隨機海洋波浪,近幾年來則致力於數據分析研究,特別是利用一創新應用數學演算法:「Hilbert-Huang Transformation(以下簡稱HHT)訊號分析演算法」研究非穩態及非線性的時間序列。在過去幾年,黃鍔院士應用「HHT」訊號分析演算法於各領域進行數據資料分析:如非線性海洋波浪演進數據、地震訊號結構反應、橋梁結構安全監測、生物訊號、氣候環境變遷(如全球溫度變化、南極冰河變化、太陽能輻射變化)等。

由於此項訊號分析演算法的發明,黃鍔院士於1998年、2003年、2004年榮獲美國航空暨太空總署NASA頒發的傑出太空表現獎。1999年榮獲聯邦政府專業領袖獎、2001年榮獲聯邦實驗室發展獎、2006年榮獲美國科學與環境服務獎。

HHT應用領域非常廣,根據美國航空暨太空總署之統計至少包含有:醫學、聲學、振動噪音、環境、工業應用、結構土木工程、流體動力學、企管財務分析。本方法為黃鍔博士之重要發明與NASA史上所研發之最重要的應用數學演算法之一。

附加檔案:
[光電所演講] Key requirements for achieving high-efficiency, multi-junction solar cells using a-Si:H, a-SiGe:H, and nc-Si:H on flexible substrates Dr. Jeffrey YangVice President 2011-03-18 13:30 博理101演講廳
[光電所演講] Key requirements for achieving high-efficiency, multi-junction solar cells using a-Si:H, a-SiGe:H, and nc-Si:H on flexible substrates 演講者:Dr. Jeffrey YangVice President|R&D of United Solar Ovonic
時間:Date:2011-03-18|TIme:13:30
地點:博理101演講廳
主辦單位:光電所
協辦單位:
聯絡人:姚力琪小姐
聯絡電話:02-33663587
演講內容:
附加檔案:
Three-dimensional Intergrated Circuits (3D-ICs) Design, EDA, and Architecture Prof. Yuan Xie 2011-02-25 14:00 電機二館105室
Three-dimensional Intergrated Circuits (3D-ICs) Design, EDA, and Architecture 演講者:Prof. Yuan Xie|Computer Science & Engineering Dept. Pennsylvania State University
時間:Date:2011-02-25|TIme:14:00
地點:電機二館105室
主辦單位:電子所
協辦單位:
聯絡人:邱玉霜
聯絡電話:shuang@cc.ee.ntu.edu.tw
演講內容:
講者介紹:Yuan Xie received the B.S. degree in electronic engineering from Tsinghua University, Beijing, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Princeton University in 1999 and 2002, respectively. He is currently Associate Professor in Computer Science and Engineering department at the Pennsylvania State University. Before Joining Penn State in Fall 2003, he was with IBM Microelectronic Division’s Worldwide Design Center.  Prof. Xie is a recipient of the National Science Foundation Early Faculty (CAREER) award, the SRC Inventor Recognition Award, IBM Faculty Award, and several Best Paper Award and Best Paper Award Nominations at IEEE/ACM conferences. He has published more than 100 research papers in journals and refereed conference proceedings, in the area of EDA, computer architecture, VLSI circuit designs, and embedded systems. His current research projects include: three-dimensional integrated circuits (3D ICs) design, EDA, and architecture; emerging memory technologies; low power and thermal-aware design; reliable circuits and architectures; and embedded system synthesis. He is currently Associate Editor for ACM Journal of Emerging Technologies in Computing Systems (JETC), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), IEEE Design and Test of Computers, IET Computers and Digital Techniques (IET CDT).

演講大綱:
3D Integration emerges as an attractive option to sustain Moore’s law as well as to enable More-than-Moore. This talk will present an overview of recent research progress in 3D IC designs, including both design tools perspective and architecture design perspective. It will also emphasize the following research directions for future 3D IC design: Design automation and test techniques and methodologies for 3D designs are imperative to realize 3D integration; Novel architectures and design space exploration at the architectural level are also essential to leverage 3D integration technologies for performance gain; Possible "killer" application for 3D integration (e.g., what application could dramatically benefit from 3D stacking technology or what novel applications are enabled by 3D technology.)

 
附加檔案:
DFT Challenges at NVIDIA Dan SmithDirector 2011-01-24 17:30 BL113
DFT Challenges at NVIDIA 演講者:Dan SmithDirector|Hardware Engineering
時間:Date:2011-01-24|TIme:17:30
地點:BL113
主辦單位:電子所
協辦單位:
聯絡人:李建模教授
聯絡電話:cmli@cc.ee.ntu.edu.tw
演講內容:
摘要:
DFT technologies we use
why this is critical to our success
where it fits into the overall development flow
what kind of activities DFT engineers will perform.

Speaker's Bio:
擁有20年以上硬體設計流程相關經驗,曾任職於Apple、Motorola等國際知名外商公司多年。
現任NVIDIA硬體設計流程部門處長,負責Design Methodology開發。
附加檔案:
Iterative Receiver Algorithms: a Tutorial Prof. Dr. sc. techn. Heinrich Meyr 2011-01-17 14:00 博理館201室
Iterative Receiver Algorithms: a Tutorial 演講者:Prof. Dr. sc. techn. Heinrich Meyr|RWTH Aachen University, The Institute for Integrated Signal Processing Systems
時間:Date:2011-01-17|TIme:14:00
地點:博理館201室
主辦單位:臺大資電中心、電子所
協辦單位:臺大電機系、電信所、臺大-聯發科技無線研究實驗室、系統晶片中心、國研院晶片系統設計中心
聯絡人:劉小鳳
聯絡電話:hsiaofeng@cc.ee.ntu.edu.tw
演講內容:
Prof. Dr. sc. techn. Heinrich Meyr(RWTH Aachen University, The Institute for Integrated Signal Processing Systems應邀來台參訪,此演講活動完全免費入場,機會難得,敬請把握!
 

 
此演講有配合電子所參加演講集點活動,現場核發集點卡,全程參加可核章集點,
已領有集點卡的同學,請記得攜帶您的集點卡來核章!
 
臺大電子所鼓勵學生參加演講活動100年1-6月集點辦法
1.  本活動參加對象:電子所在學同學。
2.  集點卡索取地點:電子所所辦和演講會場。
3.  集點卡限本人使用,姓名與學號一經寫定不得塗改。
4.  每次進場、離場均需核章,遲到或早退將不予核章,事後亦不予補章。
5.  凡參加電子所主辦、協辦之課程外演講,均可累積點數,全程參與者,每次核發乙點。每張集點卡可累計3點,累計滿3點之集點卡即取得摸彩資格,可多參加演講活動累計多張集點卡以增加中獎機會,相關獎項如附件。每位學生頭獎和貳獎限得乙獎。
6.  凡累計滿3點之集點卡,請於100年6月30日(四)下班前前將集點卡投入所辦之摸彩箱,電子所將於7月初擇日舉行公開抽獎(詳細時間地點將於公告5月底前公告),不在場者視同棄權
7.  本次辦理期間為100年1月3日(一)~6月30日(四)
 
附件
頭獎   iPad 一名 (或價值約NT$15,000之等值獎項)
貳獎   數位相機一台(價值約NT$7,500)
参獎   金石堂圖書禮券NT$300 若干名
附加檔案: